C Specification

To write a 32-bit marker value into a buffer as a pipelined operation, call:

// Provided by VK_KHR_synchronization2 with VK_AMD_buffer_marker
void vkCmdWriteBufferMarker2AMD(
    VkCommandBuffer                             commandBuffer,
    VkPipelineStageFlags2KHR                    stage,
    VkBuffer                                    dstBuffer,
    VkDeviceSize                                dstOffset,
    uint32_t                                    marker);

Parameters

  • commandBuffer is the command buffer into which the command will be recorded.

  • stage specifies the pipeline stage whose completion triggers the marker write.

  • dstBuffer is the buffer where the marker will be written.

  • dstOffset is the byte offset into the buffer where the marker will be written.

  • marker is the 32-bit value of the marker.

Description

The command will write the 32-bit marker value into the buffer only after all preceding commands have finished executing up to at least the specified pipeline stage. This includes the completion of other preceding vkCmdWriteBufferMarker2AMD commands so long as their specified pipeline stages occur either at the same time or earlier than this command’s specified pipelineStage.

While consecutive buffer marker writes with the same pipelineStage parameter implicitly complete in submission order, memory and execution dependencies between buffer marker writes and other operations must still be explicitly ordered using synchronization commands. The access scope for buffer marker writes falls under the VK_ACCESS_TRANSFER_WRITE_BIT, and the pipeline stages for identifying the synchronization scope must include both pipelineStage and VK_PIPELINE_STAGE_TRANSFER_BIT.

Note

Similar to vkCmdWriteTimestamp2KHR, if an implementation is unable to write a marker at any specific pipeline stage, it may instead do so at any logically later stage.

Note

Implementations may only support a limited number of pipelined marker write operations in flight at a given time. Thus an excessive number of marker write operations may degrade command execution performance.

Valid Usage
  • VUID-vkCmdWriteBufferMarker2AMD-stage-03929
    If the geometry shaders feature is not enabled, stage must not contain VK_PIPELINE_STAGE_2_GEOMETRY_SHADER_BIT_KHR

  • VUID-vkCmdWriteBufferMarker2AMD-stage-03930
    If the tessellation shaders feature is not enabled, stage must not contain VK_PIPELINE_STAGE_2_TESSELLATION_CONTROL_SHADER_BIT_KHR or VK_PIPELINE_STAGE_2_TESSELLATION_EVALUATION_SHADER_BIT_KHR

  • VUID-vkCmdWriteBufferMarker2AMD-stage-03931
    If the conditional rendering feature is not enabled, stage must not contain VK_PIPELINE_STAGE_2_CONDITIONAL_RENDERING_BIT_EXT

  • VUID-vkCmdWriteBufferMarker2AMD-stage-03932
    If the fragment density map feature is not enabled, stage must not contain VK_PIPELINE_STAGE_2_FRAGMENT_DENSITY_PROCESS_BIT_EXT

  • VUID-vkCmdWriteBufferMarker2AMD-stage-03933
    If the transform feedback feature is not enabled, stage must not contain VK_PIPELINE_STAGE_2_TRANSFORM_FEEDBACK_BIT_EXT

  • VUID-vkCmdWriteBufferMarker2AMD-stage-03934
    If the mesh shaders feature is not enabled, stage must not contain VK_PIPELINE_STAGE_2_MESH_SHADER_BIT_NV

  • VUID-vkCmdWriteBufferMarker2AMD-stage-03935
    If the task shaders feature is not enabled, stage must not contain VK_PIPELINE_STAGE_2_TASK_SHADER_BIT_NV

  • VUID-vkCmdWriteBufferMarker2AMD-stage-03936
    If the shading rate image feature is not enabled, stage must not contain VK_PIPELINE_STAGE_2_SHADING_RATE_IMAGE_BIT_NV

  • VUID-vkCmdWriteBufferMarker2AMD-synchronization2-03893
    The synchronization2 feature must be enabled

  • VUID-vkCmdWriteBufferMarker2AMD-stage-03894
    stage must include only a single pipeline stage

  • VUID-vkCmdWriteBufferMarker2AMD-stage-03895
    stage must include only stages that are valid for the queue family that was used to create the command pool that commandBuffer was allocated from

  • VUID-vkCmdWriteBufferMarker2AMD-dstOffset-03896
    dstOffset must be less than or equal to the size of dstBuffer minus 4.

  • VUID-vkCmdWriteBufferMarker2AMD-dstBuffer-03897
    dstBuffer must have been created with the VK_BUFFER_USAGE_TRANSFER_DST_BIT usage flag

  • VUID-vkCmdWriteBufferMarker2AMD-dstBuffer-03898
    If dstBuffer is non-sparse then it must be bound completely and contiguously to a single VkDeviceMemory object

  • VUID-vkCmdWriteBufferMarker2AMD-dstOffset-03899
    dstOffset must be a multiple of 4

Valid Usage (Implicit)
  • VUID-vkCmdWriteBufferMarker2AMD-commandBuffer-parameter
    commandBuffer must be a valid VkCommandBuffer handle

  • VUID-vkCmdWriteBufferMarker2AMD-stage-parameter
    stage must be a valid combination of VkPipelineStageFlagBits2KHR values

  • VUID-vkCmdWriteBufferMarker2AMD-stage-requiredbitmask
    stage must not be 0

  • VUID-vkCmdWriteBufferMarker2AMD-dstBuffer-parameter
    dstBuffer must be a valid VkBuffer handle

  • VUID-vkCmdWriteBufferMarker2AMD-commandBuffer-recording
    commandBuffer must be in the recording state

  • VUID-vkCmdWriteBufferMarker2AMD-commandBuffer-cmdpool
    The VkCommandPool that commandBuffer was allocated from must support transfer, graphics, or compute operations

  • VUID-vkCmdWriteBufferMarker2AMD-commonparent
    Both of commandBuffer, and dstBuffer must have been created, allocated, or retrieved from the same VkDevice

Host Synchronization
  • Host access to commandBuffer must be externally synchronized

  • Host access to the VkCommandPool that commandBuffer was allocated from must be externally synchronized

Command Properties
Command Buffer Levels Render Pass Scope Supported Queue Types Pipeline Type

Primary
Secondary

Both

Transfer
Graphics
Compute

Transfer

See Also

Document Notes

For more information, see the Vulkan Specification

This page is extracted from the Vulkan Specification. Fixes and changes should be made to the Specification, not directly.

Copyright 2014-2021 The Khronos Group Inc.

SPDX-License-Identifier: CC-BY-4.0