VkMemoryBarrier2KHR(3)

C Specification

The VkMemoryBarrier2KHR structure is defined as:

// Provided by VK_KHR_synchronization2
typedef struct VkMemoryBarrier2KHR {
    VkStructureType             sType;
    const void*                 pNext;
    VkPipelineStageFlags2KHR    srcStageMask;
    VkAccessFlags2KHR           srcAccessMask;
    VkPipelineStageFlags2KHR    dstStageMask;
    VkAccessFlags2KHR           dstAccessMask;
} VkMemoryBarrier2KHR;

Members

sType is the type of this structure.
pNext is NULL or a pointer to a structure extending this structure.
srcStageMask is a VkPipelineStageFlags2KHR mask of pipeline stages to be included in the first synchronization scope.
srcAccessMask is a VkAccessFlags2KHR mask of access flags to be included in the first access scope.
dstStageMask is a VkPipelineStageFlags2KHR mask of pipeline stages to be included in the second synchronization scope.
dstAccessMask is a VkAccessFlags2KHR mask of access flags to be included in the second access scope.

Description

This structure defines a memory dependency affecting all device memory.

The first synchronization scope and access scope described by this structure include only operations and memory accesses specified by srcStageMask and srcAccessMask.

The second synchronization scope and access scope described by this structure include only operations and memory accesses specified by dstStageMask and dstAccessMask.

Valid Usage

VUID-VkMemoryBarrier2KHR-srcStageMask-03929
If the geometry shaders feature is not enabled, srcStageMask must not contain VK_PIPELINE_STAGE_2_GEOMETRY_SHADER_BIT_KHR
VUID-VkMemoryBarrier2KHR-srcStageMask-03930
If the tessellation shaders feature is not enabled, srcStageMask must not contain VK_PIPELINE_STAGE_2_TESSELLATION_CONTROL_SHADER_BIT_KHR or VK_PIPELINE_STAGE_2_TESSELLATION_EVALUATION_SHADER_BIT_KHR
VUID-VkMemoryBarrier2KHR-srcStageMask-03931
If the conditional rendering feature is not enabled, srcStageMask must not contain VK_PIPELINE_STAGE_2_CONDITIONAL_RENDERING_BIT_EXT
VUID-VkMemoryBarrier2KHR-srcStageMask-03932
If the fragment density map feature is not enabled, srcStageMask must not contain VK_PIPELINE_STAGE_2_FRAGMENT_DENSITY_PROCESS_BIT_EXT
VUID-VkMemoryBarrier2KHR-srcStageMask-03933
If the transform feedback feature is not enabled, srcStageMask must not contain VK_PIPELINE_STAGE_2_TRANSFORM_FEEDBACK_BIT_EXT
VUID-VkMemoryBarrier2KHR-srcStageMask-03934
If the mesh shaders feature is not enabled, srcStageMask must not contain VK_PIPELINE_STAGE_2_MESH_SHADER_BIT_NV
VUID-VkMemoryBarrier2KHR-srcStageMask-03935
If the task shaders feature is not enabled, srcStageMask must not contain VK_PIPELINE_STAGE_2_TASK_SHADER_BIT_NV
VUID-VkMemoryBarrier2KHR-srcStageMask-04956
If the shading rate image feature is not enabled, srcStageMask must not contain VK_PIPELINE_STAGE_2_SHADING_RATE_IMAGE_BIT_NV
VUID-VkMemoryBarrier2KHR-srcStageMask-04957
If the subpass shading feature is not enabled, srcStageMask must not contain VK_PIPELINE_STAGE_2_SUBPASS_SHADING_BIT_HUAWEI
VUID-VkMemoryBarrier2KHR-srcStageMask-04995
If the invocation mask image feature is not enabled, srcStageMask must not contain VK_PIPELINE_STAGE_2_INVOCATION_MASK_BIT_HUAWEI
VUID-VkMemoryBarrier2KHR-srcAccessMask-03900
If srcAccessMask includes VK_ACCESS_2_INDIRECT_COMMAND_READ_BIT_KHR, srcStageMask must include VK_PIPELINE_STAGE_2_DRAW_INDIRECT_BIT_KHR, VK_PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_BUILD_BIT_KHR, VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR, or VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR
VUID-VkMemoryBarrier2KHR-srcAccessMask-03901
If srcAccessMask includes VK_ACCESS_2_INDEX_READ_BIT_KHR, srcStageMask must include VK_PIPELINE_STAGE_2_INDEX_INPUT_BIT_KHR, VK_PIPELINE_STAGE_2_VERTEX_INPUT_BIT_KHR, VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR, or VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR
VUID-VkMemoryBarrier2KHR-srcAccessMask-03902
If srcAccessMask includes VK_ACCESS_2_VERTEX_ATTRIBUTE_READ_BIT_KHR, srcStageMask must include VK_PIPELINE_STAGE_2_VERTEX_ATTRIBUTE_INPUT_BIT_KHR, VK_PIPELINE_STAGE_2_VERTEX_INPUT_BIT_KHR, VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR, or VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR
VUID-VkMemoryBarrier2KHR-srcAccessMask-03903
If srcAccessMask includes VK_ACCESS_2_INPUT_ATTACHMENT_READ_BIT_KHR, srcStageMask must include VK_PIPELINE_STAGE_2_FRAGMENT_SHADER_BIT_KHR, VK_PIPELINE_STAGE_2_SUBPASS_SHADING_BIT_HUAWEI, VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR, or VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR
VUID-VkMemoryBarrier2KHR-srcAccessMask-03904
If srcAccessMask includes VK_ACCESS_2_UNIFORM_READ_BIT_KHR, srcStageMask must include VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR, VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR, or one of the VK_PIPELINE_STAGE_*_SHADER_BIT stages
VUID-VkMemoryBarrier2KHR-srcAccessMask-03905
If srcAccessMask includes VK_ACCESS_2_SHADER_SAMPLED_READ_BIT_KHR, srcStageMask must include VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR, VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR, or one of the VK_PIPELINE_STAGE_*_SHADER_BIT stages
VUID-VkMemoryBarrier2KHR-srcAccessMask-03906
If srcAccessMask includes VK_ACCESS_2_SHADER_STORAGE_READ_BIT_KHR, srcStageMask must include VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR, VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR, or one of the VK_PIPELINE_STAGE_*_SHADER_BIT stages
VUID-VkMemoryBarrier2KHR-srcAccessMask-03907
If srcAccessMask includes VK_ACCESS_2_SHADER_STORAGE_WRITE_BIT_KHR, srcStageMask must include VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR, VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR, or one of the VK_PIPELINE_STAGE_*_SHADER_BIT stages
VUID-VkMemoryBarrier2KHR-srcAccessMask-03908
If srcAccessMask includes VK_ACCESS_2_SHADER_READ_BIT_KHR, srcStageMask must include VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR, VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR, VK_PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_BUILD_BIT_KHR, or one of the VK_PIPELINE_STAGE_*_SHADER_BIT stages
VUID-VkMemoryBarrier2KHR-srcAccessMask-03909
If srcAccessMask includes VK_ACCESS_2_SHADER_WRITE_BIT_KHR, srcStageMask must include VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR, VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR, or one of the VK_PIPELINE_STAGE_*_SHADER_BIT stages
VUID-VkMemoryBarrier2KHR-srcAccessMask-03910
If srcAccessMask includes VK_ACCESS_2_COLOR_ATTACHMENT_READ_BIT_KHR, srcStageMask must include VK_PIPELINE_STAGE_2_COLOR_ATTACHMENT_OUTPUT_BIT_KHR VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR, or VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR
VUID-VkMemoryBarrier2KHR-srcAccessMask-03911
If srcAccessMask includes VK_ACCESS_2_COLOR_ATTACHMENT_WRITE_BIT_KHR, srcStageMask must include VK_PIPELINE_STAGE_2_COLOR_ATTACHMENT_OUTPUT_BIT_KHR VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR, or VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR
VUID-VkMemoryBarrier2KHR-srcAccessMask-03912
If srcAccessMask includes VK_ACCESS_2_DEPTH_STENCIL_ATTACHMENT_READ_BIT_KHR, srcStageMask must include VK_PIPELINE_STAGE_2_EARLY_FRAGMENT_TESTS_BIT_KHR, VK_PIPELINE_STAGE_2_LATE_FRAGMENT_TESTS_BIT_KHR, VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR, or VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR
VUID-VkMemoryBarrier2KHR-srcAccessMask-03913
If srcAccessMask includes VK_ACCESS_2_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT_KHR, srcStageMask must include VK_PIPELINE_STAGE_2_EARLY_FRAGMENT_TESTS_BIT_KHR, VK_PIPELINE_STAGE_2_LATE_FRAGMENT_TESTS_BIT_KHR, VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR, or VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR
VUID-VkMemoryBarrier2KHR-srcAccessMask-03914
If srcAccessMask includes VK_ACCESS_2_TRANSFER_READ_BIT_KHR, srcStageMask must include VK_PIPELINE_STAGE_2_COPY_BIT_KHR, VK_PIPELINE_STAGE_2_BLIT_BIT_KHR, VK_PIPELINE_STAGE_2_RESOLVE_BIT_KHR, VK_PIPELINE_STAGE_2_ALL_TRANSFER_BIT_KHR, VK_PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_BUILD_BIT_KHR, or VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR
VUID-VkMemoryBarrier2KHR-srcAccessMask-03915
If srcAccessMask includes VK_ACCESS_2_TRANSFER_WRITE_BIT_KHR, srcStageMask must include VK_PIPELINE_STAGE_2_COPY_BIT_KHR, VK_PIPELINE_STAGE_2_BLIT_BIT_KHR, VK_PIPELINE_STAGE_2_RESOLVE_BIT_KHR, VK_PIPELINE_STAGE_2_CLEAR_BIT_KHR, VK_PIPELINE_STAGE_2_ALL_TRANSFER_BIT_KHR, VK_PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_BUILD_BIT_KHR, or VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR
VUID-VkMemoryBarrier2KHR-srcAccessMask-03916
If srcAccessMask includes VK_ACCESS_2_HOST_READ_BIT_KHR, srcStageMask must include VK_PIPELINE_STAGE_2_HOST_BIT_KHR
VUID-VkMemoryBarrier2KHR-srcAccessMask-03917
If srcAccessMask includes VK_ACCESS_2_HOST_WRITE_BIT_KHR, srcStageMask must include VK_PIPELINE_STAGE_2_HOST_BIT_KHR
VUID-VkMemoryBarrier2KHR-srcAccessMask-03918
If srcAccessMask includes VK_ACCESS_2_CONDITIONAL_RENDERING_READ_BIT_EXT, srcStageMask must include VK_PIPELINE_STAGE_2_CONDITIONAL_RENDERING_BIT_EXT, VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR, or VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR
VUID-VkMemoryBarrier2KHR-srcAccessMask-03919
If srcAccessMask includes VK_ACCESS_2_FRAGMENT_DENSITY_MAP_READ_BIT_EXT, srcStageMask must include VK_PIPELINE_STAGE_2_FRAGMENT_DENSITY_PROCESS_BIT_EXT, VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR, or VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR
VUID-VkMemoryBarrier2KHR-srcAccessMask-03920
If srcAccessMask includes VK_ACCESS_2_TRANSFORM_FEEDBACK_WRITE_BIT_EXT, srcStageMask must include VK_PIPELINE_STAGE_2_TRANSFORM_FEEDBACK_BIT_EXT, VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR, or VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR
VUID-VkMemoryBarrier2KHR-srcAccessMask-04747
If srcAccessMask includes VK_ACCESS_2_TRANSFORM_FEEDBACK_COUNTER_READ_BIT_EXT, srcStageMask must include VK_PIPELINE_STAGE_2_DRAW_INDIRECT_BIT_KHR, VK_PIPELINE_STAGE_2_TRANSFORM_FEEDBACK_BIT_EXT, VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR, or VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR
VUID-VkMemoryBarrier2KHR-srcAccessMask-03922
If srcAccessMask includes VK_ACCESS_2_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT, srcStageMask must include VK_PIPELINE_STAGE_2_TRANSFORM_FEEDBACK_BIT_EXT, VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR, or VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR
VUID-VkMemoryBarrier2KHR-srcAccessMask-03923
If srcAccessMask includes VK_ACCESS_2_SHADING_RATE_IMAGE_READ_BIT_NV, srcStageMask must include VK_PIPELINE_STAGE_2_SHADING_RATE_IMAGE_BIT_NV, VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR, or VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR
VUID-VkMemoryBarrier2KHR-srcAccessMask-04994
If srcAccessMask includes VK_ACCESS_2_INVOCATION_MASK_READ_BIT_HUAWEI, srcStageMask must include VK_PIPELINE_STAGE_2_INVOCATION_MASK_BIT_HUAWEI
VUID-VkMemoryBarrier2KHR-srcAccessMask-03924
If srcAccessMask includes VK_ACCESS_2_COMMAND_PREPROCESS_READ_BIT_NV, srcStageMask must include VK_PIPELINE_STAGE_2_COMMAND_PREPROCESS_BIT_NV or VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR
VUID-VkMemoryBarrier2KHR-srcAccessMask-03925
If srcAccessMask includes VK_ACCESS_2_COMMAND_PREPROCESS_WRITE_BIT_NV, srcStageMask must include VK_PIPELINE_STAGE_2_COMMAND_PREPROCESS_BIT_NV or VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR
VUID-VkMemoryBarrier2KHR-srcAccessMask-03926
If srcAccessMask includes VK_ACCESS_2_COLOR_ATTACHMENT_READ_NONCOHERENT_BIT_EXT, srcStageMask must include VK_PIPELINE_STAGE_2_COLOR_ATTACHMENT_OUTPUT_BIT_KHR VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR, or VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR
VUID-VkMemoryBarrier2KHR-srcAccessMask-03927
If srcAccessMask includes VK_ACCESS_2_ACCELERATION_STRUCTURE_READ_BIT_KHR, srcStageMask must include VK_PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_BUILD_BIT_KHR, VK_PIPELINE_STAGE_2_RAY_TRACING_SHADER_BIT_KHR, or VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR
VUID-VkMemoryBarrier2KHR-srcAccessMask-03928
If srcAccessMask includes VK_ACCESS_2_ACCELERATION_STRUCTURE_WRITE_BIT_KHR, srcStageMask must include VK_PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_BUILD_BIT_KHR or VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR
VUID-VkMemoryBarrier2KHR-srcAccessMask-04858
If srcAccessMask includes VK_ACCESS_2_VIDEO_DECODE_READ_BIT_KHR, srcStageMask must include VK_PIPELINE_STAGE_2_VIDEO_DECODE_BIT_KHR
VUID-VkMemoryBarrier2KHR-srcAccessMask-04859
If srcAccessMask includes VK_ACCESS_2_VIDEO_DECODE_WRITE_BIT_KHR, srcStageMask must include VK_PIPELINE_STAGE_2_VIDEO_DECODE_BIT_KHR
VUID-VkMemoryBarrier2KHR-srcAccessMask-04860
If srcAccessMask includes VK_ACCESS_2_VIDEO_ENCODE_READ_BIT_KHR, srcStageMask must include VK_PIPELINE_STAGE_2_VIDEO_ENCODE_BIT_KHR
VUID-VkMemoryBarrier2KHR-srcAccessMask-04861
If srcAccessMask includes VK_ACCESS_2_VIDEO_ENCODE_WRITE_BIT_KHR, srcStageMask must include VK_PIPELINE_STAGE_2_VIDEO_ENCODE_BIT_KHR

VUID-VkMemoryBarrier2KHR-dstStageMask-03929
If the geometry shaders feature is not enabled, dstStageMask must not contain VK_PIPELINE_STAGE_2_GEOMETRY_SHADER_BIT_KHR
VUID-VkMemoryBarrier2KHR-dstStageMask-03930
If the tessellation shaders feature is not enabled, dstStageMask must not contain VK_PIPELINE_STAGE_2_TESSELLATION_CONTROL_SHADER_BIT_KHR or VK_PIPELINE_STAGE_2_TESSELLATION_EVALUATION_SHADER_BIT_KHR
VUID-VkMemoryBarrier2KHR-dstStageMask-03931
If the conditional rendering feature is not enabled, dstStageMask must not contain VK_PIPELINE_STAGE_2_CONDITIONAL_RENDERING_BIT_EXT
VUID-VkMemoryBarrier2KHR-dstStageMask-03932
If the fragment density map feature is not enabled, dstStageMask must not contain VK_PIPELINE_STAGE_2_FRAGMENT_DENSITY_PROCESS_BIT_EXT
VUID-VkMemoryBarrier2KHR-dstStageMask-03933
If the transform feedback feature is not enabled, dstStageMask must not contain VK_PIPELINE_STAGE_2_TRANSFORM_FEEDBACK_BIT_EXT
VUID-VkMemoryBarrier2KHR-dstStageMask-03934
If the mesh shaders feature is not enabled, dstStageMask must not contain VK_PIPELINE_STAGE_2_MESH_SHADER_BIT_NV
VUID-VkMemoryBarrier2KHR-dstStageMask-03935
If the task shaders feature is not enabled, dstStageMask must not contain VK_PIPELINE_STAGE_2_TASK_SHADER_BIT_NV
VUID-VkMemoryBarrier2KHR-dstStageMask-04956
If the shading rate image feature is not enabled, dstStageMask must not contain VK_PIPELINE_STAGE_2_SHADING_RATE_IMAGE_BIT_NV
VUID-VkMemoryBarrier2KHR-dstStageMask-04957
If the subpass shading feature is not enabled, dstStageMask must not contain VK_PIPELINE_STAGE_2_SUBPASS_SHADING_BIT_HUAWEI
VUID-VkMemoryBarrier2KHR-dstStageMask-04995
If the invocation mask image feature is not enabled, dstStageMask must not contain VK_PIPELINE_STAGE_2_INVOCATION_MASK_BIT_HUAWEI
VUID-VkMemoryBarrier2KHR-dstAccessMask-03900
If dstAccessMask includes VK_ACCESS_2_INDIRECT_COMMAND_READ_BIT_KHR, dstStageMask must include VK_PIPELINE_STAGE_2_DRAW_INDIRECT_BIT_KHR, VK_PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_BUILD_BIT_KHR, VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR, or VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR
VUID-VkMemoryBarrier2KHR-dstAccessMask-03901
If dstAccessMask includes VK_ACCESS_2_INDEX_READ_BIT_KHR, dstStageMask must include VK_PIPELINE_STAGE_2_INDEX_INPUT_BIT_KHR, VK_PIPELINE_STAGE_2_VERTEX_INPUT_BIT_KHR, VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR, or VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR
VUID-VkMemoryBarrier2KHR-dstAccessMask-03902
If dstAccessMask includes VK_ACCESS_2_VERTEX_ATTRIBUTE_READ_BIT_KHR, dstStageMask must include VK_PIPELINE_STAGE_2_VERTEX_ATTRIBUTE_INPUT_BIT_KHR, VK_PIPELINE_STAGE_2_VERTEX_INPUT_BIT_KHR, VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR, or VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR
VUID-VkMemoryBarrier2KHR-dstAccessMask-03903
If dstAccessMask includes VK_ACCESS_2_INPUT_ATTACHMENT_READ_BIT_KHR, dstStageMask must include VK_PIPELINE_STAGE_2_FRAGMENT_SHADER_BIT_KHR, VK_PIPELINE_STAGE_2_SUBPASS_SHADING_BIT_HUAWEI, VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR, or VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR
VUID-VkMemoryBarrier2KHR-dstAccessMask-03904
If dstAccessMask includes VK_ACCESS_2_UNIFORM_READ_BIT_KHR, dstStageMask must include VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR, VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR, or one of the VK_PIPELINE_STAGE_*_SHADER_BIT stages
VUID-VkMemoryBarrier2KHR-dstAccessMask-03905
If dstAccessMask includes VK_ACCESS_2_SHADER_SAMPLED_READ_BIT_KHR, dstStageMask must include VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR, VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR, or one of the VK_PIPELINE_STAGE_*_SHADER_BIT stages
VUID-VkMemoryBarrier2KHR-dstAccessMask-03906
If dstAccessMask includes VK_ACCESS_2_SHADER_STORAGE_READ_BIT_KHR, dstStageMask must include VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR, VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR, or one of the VK_PIPELINE_STAGE_*_SHADER_BIT stages
VUID-VkMemoryBarrier2KHR-dstAccessMask-03907
If dstAccessMask includes VK_ACCESS_2_SHADER_STORAGE_WRITE_BIT_KHR, dstStageMask must include VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR, VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR, or one of the VK_PIPELINE_STAGE_*_SHADER_BIT stages
VUID-VkMemoryBarrier2KHR-dstAccessMask-03908
If dstAccessMask includes VK_ACCESS_2_SHADER_READ_BIT_KHR, dstStageMask must include VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR, VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR, VK_PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_BUILD_BIT_KHR, or one of the VK_PIPELINE_STAGE_*_SHADER_BIT stages
VUID-VkMemoryBarrier2KHR-dstAccessMask-03909
If dstAccessMask includes VK_ACCESS_2_SHADER_WRITE_BIT_KHR, dstStageMask must include VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR, VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR, or one of the VK_PIPELINE_STAGE_*_SHADER_BIT stages
VUID-VkMemoryBarrier2KHR-dstAccessMask-03910
If dstAccessMask includes VK_ACCESS_2_COLOR_ATTACHMENT_READ_BIT_KHR, dstStageMask must include VK_PIPELINE_STAGE_2_COLOR_ATTACHMENT_OUTPUT_BIT_KHR VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR, or VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR
VUID-VkMemoryBarrier2KHR-dstAccessMask-03911
If dstAccessMask includes VK_ACCESS_2_COLOR_ATTACHMENT_WRITE_BIT_KHR, dstStageMask must include VK_PIPELINE_STAGE_2_COLOR_ATTACHMENT_OUTPUT_BIT_KHR VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR, or VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR
VUID-VkMemoryBarrier2KHR-dstAccessMask-03912
If dstAccessMask includes VK_ACCESS_2_DEPTH_STENCIL_ATTACHMENT_READ_BIT_KHR, dstStageMask must include VK_PIPELINE_STAGE_2_EARLY_FRAGMENT_TESTS_BIT_KHR, VK_PIPELINE_STAGE_2_LATE_FRAGMENT_TESTS_BIT_KHR, VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR, or VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR
VUID-VkMemoryBarrier2KHR-dstAccessMask-03913
If dstAccessMask includes VK_ACCESS_2_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT_KHR, dstStageMask must include VK_PIPELINE_STAGE_2_EARLY_FRAGMENT_TESTS_BIT_KHR, VK_PIPELINE_STAGE_2_LATE_FRAGMENT_TESTS_BIT_KHR, VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR, or VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR
VUID-VkMemoryBarrier2KHR-dstAccessMask-03914
If dstAccessMask includes VK_ACCESS_2_TRANSFER_READ_BIT_KHR, dstStageMask must include VK_PIPELINE_STAGE_2_COPY_BIT_KHR, VK_PIPELINE_STAGE_2_BLIT_BIT_KHR, VK_PIPELINE_STAGE_2_RESOLVE_BIT_KHR, VK_PIPELINE_STAGE_2_ALL_TRANSFER_BIT_KHR, VK_PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_BUILD_BIT_KHR, or VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR
VUID-VkMemoryBarrier2KHR-dstAccessMask-03915
If dstAccessMask includes VK_ACCESS_2_TRANSFER_WRITE_BIT_KHR, dstStageMask must include VK_PIPELINE_STAGE_2_COPY_BIT_KHR, VK_PIPELINE_STAGE_2_BLIT_BIT_KHR, VK_PIPELINE_STAGE_2_RESOLVE_BIT_KHR, VK_PIPELINE_STAGE_2_CLEAR_BIT_KHR, VK_PIPELINE_STAGE_2_ALL_TRANSFER_BIT_KHR, VK_PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_BUILD_BIT_KHR, or VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR
VUID-VkMemoryBarrier2KHR-dstAccessMask-03916
If dstAccessMask includes VK_ACCESS_2_HOST_READ_BIT_KHR, dstStageMask must include VK_PIPELINE_STAGE_2_HOST_BIT_KHR
VUID-VkMemoryBarrier2KHR-dstAccessMask-03917
If dstAccessMask includes VK_ACCESS_2_HOST_WRITE_BIT_KHR, dstStageMask must include VK_PIPELINE_STAGE_2_HOST_BIT_KHR
VUID-VkMemoryBarrier2KHR-dstAccessMask-03918
If dstAccessMask includes VK_ACCESS_2_CONDITIONAL_RENDERING_READ_BIT_EXT, dstStageMask must include VK_PIPELINE_STAGE_2_CONDITIONAL_RENDERING_BIT_EXT, VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR, or VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR
VUID-VkMemoryBarrier2KHR-dstAccessMask-03919
If dstAccessMask includes VK_ACCESS_2_FRAGMENT_DENSITY_MAP_READ_BIT_EXT, dstStageMask must include VK_PIPELINE_STAGE_2_FRAGMENT_DENSITY_PROCESS_BIT_EXT, VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR, or VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR
VUID-VkMemoryBarrier2KHR-dstAccessMask-03920
If dstAccessMask includes VK_ACCESS_2_TRANSFORM_FEEDBACK_WRITE_BIT_EXT, dstStageMask must include VK_PIPELINE_STAGE_2_TRANSFORM_FEEDBACK_BIT_EXT, VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR, or VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR
VUID-VkMemoryBarrier2KHR-dstAccessMask-04747
If dstAccessMask includes VK_ACCESS_2_TRANSFORM_FEEDBACK_COUNTER_READ_BIT_EXT, dstStageMask must include VK_PIPELINE_STAGE_2_DRAW_INDIRECT_BIT_KHR, VK_PIPELINE_STAGE_2_TRANSFORM_FEEDBACK_BIT_EXT, VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR, or VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR
VUID-VkMemoryBarrier2KHR-dstAccessMask-03922
If dstAccessMask includes VK_ACCESS_2_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT, dstStageMask must include VK_PIPELINE_STAGE_2_TRANSFORM_FEEDBACK_BIT_EXT, VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR, or VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR
VUID-VkMemoryBarrier2KHR-dstAccessMask-03923
If dstAccessMask includes VK_ACCESS_2_SHADING_RATE_IMAGE_READ_BIT_NV, dstStageMask must include VK_PIPELINE_STAGE_2_SHADING_RATE_IMAGE_BIT_NV, VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR, or VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR
VUID-VkMemoryBarrier2KHR-dstAccessMask-04994
If dstAccessMask includes VK_ACCESS_2_INVOCATION_MASK_READ_BIT_HUAWEI, dstStageMask must include VK_PIPELINE_STAGE_2_INVOCATION_MASK_BIT_HUAWEI
VUID-VkMemoryBarrier2KHR-dstAccessMask-03924
If dstAccessMask includes VK_ACCESS_2_COMMAND_PREPROCESS_READ_BIT_NV, dstStageMask must include VK_PIPELINE_STAGE_2_COMMAND_PREPROCESS_BIT_NV or VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR
VUID-VkMemoryBarrier2KHR-dstAccessMask-03925
If dstAccessMask includes VK_ACCESS_2_COMMAND_PREPROCESS_WRITE_BIT_NV, dstStageMask must include VK_PIPELINE_STAGE_2_COMMAND_PREPROCESS_BIT_NV or VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR
VUID-VkMemoryBarrier2KHR-dstAccessMask-03926
If dstAccessMask includes VK_ACCESS_2_COLOR_ATTACHMENT_READ_NONCOHERENT_BIT_EXT, dstStageMask must include VK_PIPELINE_STAGE_2_COLOR_ATTACHMENT_OUTPUT_BIT_KHR VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR, or VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR
VUID-VkMemoryBarrier2KHR-dstAccessMask-03927
If dstAccessMask includes VK_ACCESS_2_ACCELERATION_STRUCTURE_READ_BIT_KHR, dstStageMask must include VK_PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_BUILD_BIT_KHR, VK_PIPELINE_STAGE_2_RAY_TRACING_SHADER_BIT_KHR, or VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR
VUID-VkMemoryBarrier2KHR-dstAccessMask-03928
If dstAccessMask includes VK_ACCESS_2_ACCELERATION_STRUCTURE_WRITE_BIT_KHR, dstStageMask must include VK_PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_BUILD_BIT_KHR or VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR
VUID-VkMemoryBarrier2KHR-dstAccessMask-04858
If dstAccessMask includes VK_ACCESS_2_VIDEO_DECODE_READ_BIT_KHR, dstStageMask must include VK_PIPELINE_STAGE_2_VIDEO_DECODE_BIT_KHR
VUID-VkMemoryBarrier2KHR-dstAccessMask-04859
If dstAccessMask includes VK_ACCESS_2_VIDEO_DECODE_WRITE_BIT_KHR, dstStageMask must include VK_PIPELINE_STAGE_2_VIDEO_DECODE_BIT_KHR
VUID-VkMemoryBarrier2KHR-dstAccessMask-04860
If dstAccessMask includes VK_ACCESS_2_VIDEO_ENCODE_READ_BIT_KHR, dstStageMask must include VK_PIPELINE_STAGE_2_VIDEO_ENCODE_BIT_KHR
VUID-VkMemoryBarrier2KHR-dstAccessMask-04861
If dstAccessMask includes VK_ACCESS_2_VIDEO_ENCODE_WRITE_BIT_KHR, dstStageMask must include VK_PIPELINE_STAGE_2_VIDEO_ENCODE_BIT_KHR

Valid Usage (Implicit)

VUID-VkMemoryBarrier2KHR-sType-sType
sType must be VK_STRUCTURE_TYPE_MEMORY_BARRIER_2_KHR
VUID-VkMemoryBarrier2KHR-srcStageMask-parameter
srcStageMask must be a valid combination of VkPipelineStageFlagBits2KHR values
VUID-VkMemoryBarrier2KHR-srcAccessMask-parameter
srcAccessMask must be a valid combination of VkAccessFlagBits2KHR values
VUID-VkMemoryBarrier2KHR-dstStageMask-parameter
dstStageMask must be a valid combination of VkPipelineStageFlagBits2KHR values
VUID-VkMemoryBarrier2KHR-dstAccessMask-parameter
dstAccessMask must be a valid combination of VkAccessFlagBits2KHR values

Document Notes

For more information, see the Vulkan Specification

This page is extracted from the Vulkan Specification. Fixes and changes should be made to the Specification, not directly.

Copyright

SPDX-License-Identifier: CC-BY-4.0

VkMemoryBarrier2KHR(3) Manual Page

Name

C Specification

Members

Description

See Also

Document Notes

Copyright