The SYCL Compiler and Runtimes 2019-09 release allow OpenCL offloading to accelerators (GPU/FPGA). Some OpenCLCL/SYCL FPGA extensions are now supported along with support for dumping the SYCL task graph to JSON. Lots of other improvements and fixes are included on the GitHub release page.
Alibaba’s datacenter uses Xilinx FPGAs to accelerate billions of transactions for shoppers and Microsoft, in a recent announcement, said it would deploy Xilinx in its datacenter as well. This is good news for OpenCL, as Xilinx FPGA acceleration includes support for high-level programming languages and tools, including C, C++, and OpenCL.
Nallatech and BittWare have announced their FPGA products supporting OpenCL-based tool flows for Xilinx and Intel will be marketed under the BittWare brand, part of Molex. Customers will be able to program applications using traditional HDL or higher abstraction C, C++ and OpenCL-based tool flows. Read the full press release. Nallatech also announced it will deliver its family of OpenCL-compatible accelerator cards featuring Altera Stratix V FPGAs to the High Performance Computing (HPC) market. More on this here.
Recent work from Boston University has shown that with key optimizations that leverage OpenCL on Arria 10 FPGAs for 3D fast fourier transforms (FFTs), a common HPC workload, the performance can beat out FFT specific IP cores as well as GPU and CPU implementations of the same problem.
Enterprises should find it easier to tap the benefits of FPGAs now that Dell EMC and Fujitsu are putting Intel Arria 10 GX Programmable Acceleration Cards into off-the-shelf servers for the data center. The Arria 10 GX cards offers the Intel FPGA SDK for OpenCL to help ease programming hurdles. Xilinx has also been building up the software stack for its own FPGA product families, and recently announced what it calls a new category of programmable chip – the Adaptive Compute Acceleration Platform (ACAP). It says that developers can work with ACAPS using standard tools like C/C++, OpenCL, and Python.
Hybrid CPU-FPGA devices are expected to see widespread adoption. Intel is concentrating on the programming environment so the same tools will be used whether the CPUs and FPGAs are discrete or hybrid in the same socket. This is called the Acceleration Stack for Intel, and it is a complete programming environment that is based on OpenCL, the common higher level programming language that is converged to Verilog and VHDL for FPGAs. Learn more about the roadmap Intel has working on.
Xilinx, Inc announced expansion into a wide range of vision guided machine learning applications with the Xilinx reVISION stack. Developers with limited hardware expertise can use a C/C++/OpenCL development flow with industry-standard frameworks and libraries like Caffe and OpenCV to develop embedded vision applications on a single Zynq SoC or MPSoC. For application level development, Xilinx supports industry-standard frameworks including Caffe for machine learning and OpenVX for computer vision.
Amazon recently announced a developer preview of their new F1 instance. Equipped with Intel Broadwell E5 2686 v4 processors (2.3 GHz base speed, 2.7 GHz Turbo mode on all cores, and 3.0 GHz Turbo mode on one core), up to 976 GB of memory, up to 4 TB of NVMe SSD storage, and one to eight FPGAs, the F1 instances provide you with plenty of resources to complement your core, FPGA-based logic. The specs on the Xilinx FPGA are: Xilinx UltraScale+ VU9P fabricated using a 16 nm process; 64 GiB of ECC-protected memory on a 288-bit wide bus (four DDR4 channels); Dedicated PCIe x16 interface to the CPU; Approximately 2.5 million logic elements; Approximately 6,800 Digital Signal Processing (DSP) engines; Virtual JTAG interface for debugging.
S2C Inc. has announced the development of a new family of Arria 10 Prodigy FPGA Prototyping Logic Modules based on Altera’s Arria 10 1150GX FPGA. The Arria 10 Prodigy Logic Module includes compatibility with Altera’s Software Development Kit (SDK) for OpenCL allowing easy implementation for HPC applications.
Inspur and Khronos Member Intel announced partnership on an R&D project—the Field Programmable Gate Array (FPGA) accelerator card F10A, at the SC16. This is a high density and high performance FPGA card based on OpenCL.
Using OpenCL, programmers can utilize FPGAs with C, or other familiar high- level programming languages, instead of hardware-specific language. At SC16, one of the major issues for discussion is optimizing OpenCL kernels for high-performance computing.
Nimbix announced the availability of the Xilinx SDAccel development environment for on-demand development, testing, and deployment of FPGA-accelerated workflows in the Nimbix Cloud, powered by JARVICE. The SDAccel development environment combines the industry’s first architecturally optimizing compiler supporting any combination of OpenCL, C, and C++ kernels, along with libraries, development boards and industry standard development and run‐time experience for FPGAs.
Altera Corporation ALTR, -0.44% is demonstrating programmable logic-based security and system acceleration solutions for military grid communications, data centers, satellite communications and radar systems at MILCOM 2015 in Tampa, Florida, from October 26 to 28, 2015. Demonstrations from Altera and its ecosystem partners include the following technologies: A synthetic aperture radar (SAR) back-projection algorithm running on an Altera 20 nm Arria® 10 FPGA, using the Altera OpenCL SDK flow and hardened IEEE 754-compliant DSP blocks for radar back-end processing; Several complete cognitive radio solution demonstrations from front-end tactical handhelds/portables to rack-mount systems, using the RedHawk SDR architecture and hardware acceleration with an OpenCL flow.
Altera Corporation released its Quartus II software v14.1 featuring expanded support for Arria 10 FPGAs and SoCs, the FPGA industry’s only devices with hardened floating point DSP blocks and the industry’s only 20 nm SoC FPGAs that integrate ARM processors. Altera’s latest software release provides immediate support for the hardened floating point DSP blocks integrated in Arria 10 FPGAs and SoCs. Users can choose between three unique DSP design entry flows and achieve up to an industry-leading 1.5 TFLOPS of DSP performance. These design flows include OpenCL for software programmers, DSP Builder for model-based designers and hardware description language (HDL) flows for traditional FPGA designers.