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An Introduction to OpenCL for Altera FPGAs webinar

An informative 25 minute introduction on how to program Altera FPGAs with OpenCL. Presented by Acceleware, the webinar begins with an overview of the OpenCL programming model and data parallelism, before discussing simple OpenCL syntax, kernels and memory spaces. The second part of the webinar examines how OpenCL is mapped to Altera FPGA architecture and how to compile an OpenCL kernel. The presentation concludes with a summary of OpenCL optimizations techniques.
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Altera to demonstrate OpenCL at the Intel Developers Forum (IDF14) today

Altera is demonstrating several advanced reconfigurable logic technologies at the Intel Developers Forum (IDF) 2014 that showcase how its FPGA-based solutions are advancing the capabilities of software-defined data centers and high-performance computing applications. The Financial Model Acceleration with FPGAs demonstration uses OpenCL to efficiently implement multiple kernels on an FPGA performing a Monte Carlo simulation to price options. Utilizing the OpenCL standard on a massively parallel FPGA architecture provides an effective solution for system acceleration, offering significantly higher performance at much lower power versus GPUs.
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Altera SDK for OpenCL Recognized as Design Tool of the Year at the 2014 Elektra Awards

Altera Corporation announced Electronics Weekly magazine selected the Altera SDK for OpenCL as its design tool of the year at the annual Elektra European Electronics Industry Awards gala in London. These accolades represent the latest in a series of awards and recognitions the Altera SDK for OpenCL has received since its release in 2012. Today, Altera offers the industry's only OpenCL-conformant solution that allows software programmers to easily implement OpenCL applications on FPGA accelerators.
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Altera Quartus II Software v14.1 Enables TFLOPS Performance - includes OpenCL

Altera Corporation released its Quartus II software v14.1 featuring expanded support for Arria 10 FPGAs and SoCs, the FPGA industry's only devices with hardened floating point DSP blocks and the industry's only 20 nm SoC FPGAs that integrate ARM processors. Altera's latest software release provides immediate support for the hardened floating point DSP blocks integrated in Arria 10 FPGAs and SoCs. Users can choose between three unique DSP design entry flows and achieve up to an industry-leading 1.5 TFLOPS of DSP performance. These design flows include OpenCL for software programmers, DSP Builder for model-based designers and hardware description language (HDL) flows for traditional FPGA designers.
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