OpenCL tagged news

Be sure to join AJ Guillon, Yetiware and Yassine Hariri, PhD, CMC Microsystems tomorrow November 8th for the webinar 'Introducing HCMP'. As heterogeneity increases, the gap between the application layer and the hardware layer increased as well. To reduce this gap, we introduce a heterogeneous computing middleware platform (HCMP), which provides middleware that significantly reduces the complexity of developing industrial-strength heterogeneous computing software. Complex tasks such as multi-device memory management, device I/O, kernel scheduling, and dependency management are handled by the platform so that users can focus on writing their applications instead of adhering to complicated specifications.

Join CMC Microsystems and AJ Guillon, chair of the Khronos OpenCL Safety Critical (SC) TSG and founder of YetiWare, on November 8th. This webinar will discuss how to reduce the gap between the application layer and the hardware layer by introducing a heterogeneous computing middleware platform (HCMP), which provides middleware that significantly reduces the complexity of developing industrial-strength heterogeneous computing software using an OpenCL programming model.

Intel to Introduce New CPU-FPGA Hybrid Chip Supported by Acceleration Stack and OpenCLLast year, Intel acquired FPGA-focused Khronos member Altera. Intel has now announced a new line of hybrid chips that combine FPGAs with their well-known CPUs. One of the more interesting aspects of the new Intel FPGA ecosystem is the Acceleration Stack, an OpenCL based programming environment that can be used by developers for hybrid cards or discrete cards, including FPGAs, CPUs, and GPUs. The stack abstracts the programming required for the FPGAs to streamline and speed up development for accelerators and applications being used. Additionally, it allows for code to be reusable — porting between FPGAs/GPU/CPU should be possible without major changes. OpenCL, a C based programming language, will. This is quite the opposite of what had been available when Intel released the E600C seven years ago.

Hybrid CPU-FPGA devices are expected to see widespread adoption. Intel is concentrating on the programming environment so the same tools will be used whether the CPUs and FPGAs are discrete or hybrid in the same socket. This is called the Acceleration Stack for Intel, and it is a complete programming environment that is based on OpenCL, the common higher level programming language that is converged to Verilog and VHDL for FPGAs. Learn more about the roadmap Intel has working on.

ComputeCpp CE for Windows brings SYCL to Windows and Visual StudioCodeplay has announced that ComputeCpp Community Edition is now available on Windows. It is now possible to develop SYCL applications using Windows and Visual Studio. The Windows release of ComputeCpp CE currently supports Windows 7 or 10 and can be used with Visual Studio 2015. Similar to our Linux version, the hardware you want to use with ComputeCpp you is required to have SPIR OpenCL drivers in order to be supported.

IWOCL 2018 - The 6th International Workshop on OpenCLAnnouncing that the 6th International Workshop on OpenCL will take place on the 14-16 May, 2018 at St Catherine's College, Oxford, UK and that the Call for Submissions is now open. Submissions related to any aspect of using OpenCL (including SYCL, Vulkan Compute and OpenCL based libraries) are of interest, including (but not limited to): case-studies of their use in applications, software tools, programming methods, debugging, performance analysis, and integration.

The Xilinx software defined development environment, SDAccel, is now available on Amazon Web Services for use with Amazon Elastic Compute Cloud F1 instances. SDAccel automates the acceleration of software application written in C, C++ or OpenCL by building application-specific FPGA kernels for Amazon EC2 F1.

A pan-European project has started this month to bring together the technologies needed for exascale computing, tackling the key challenge of power usage. The project started this month, bringing together three existing exascale projects on FPGA accelerators, interconnect and 3D chip technologies to reach performance of 10^18 operations, 10 times that of today's fasest supercomputers. At the University of Manchester they are working on OpenCL as the programming model to configure modules that can be plugged into a system as an HPC accelerator.

Renesas Electronics announced their collaboration to deliver ComputeAorta™, Codeplay’s OpenCL open standard-based software framework for Renesas R-Car system-on-chips (SoCs). The new framework is designed to support software development for the R-Car’s latest image recognition IP, the IMP-X5, a multi-threading core optimized for computer vision and cognitive processing. Codeplay will also provide R-Car with ComputeCpp™, an implementation of the SYCL™ open standard, enabling single source C++ software for high level and object-oriented programming. The result of this collaboration provides developers with standard software development tools and support for a wide range of open source computer vision or open source deep learning software, such as TensorFlow™ library.

Codeplay announces SPIR-V support for ComputeCpp in v0.3.0. This beta implementation of SPIR-V for OpenCL support means that developers can use SYCL and ComputeCpp to develop for any OpenCL hardware that includes a driver that consumes SPIR-V.

The landscape of APIs for accelerating vision and neural network software using specialized processors continues to rapidly evolve. Many industry-standard APIs, such as OpenCL and OpenVX, are being upgraded to increasingly focus on deep learning, and the industry is rapidly adopting the new generation of low-level, explicit GPU APIs, such as Vulkan, that tightly integrate graphics and compute. Neil Trevett presented the "Vision Acceleration API Landscape: Options and Trade-offs" tutorial at the May 2017 Embedded Vision Summit.