OpenCL tagged news

Neil Trevett, Khronos Group President and Radhakrishna Giduthuri, Software Architecture and Compute Performance Acceleration at AMD, spoke at two Khronos related events this past week. Neils presented was an update on the Khronos Standards for Vision and Machine Learning which covered Khronos Standards OpenVX, NNEF, OpenCL, SYCL and Vulkan. Radhakrishna presented Standards for Neural Networks Acceleration and Deployment covered Khronos Standards OpenVX and NNEF. The slides from both presentations are now online.

The Khronos Group announces the ratification and public release of the finalized SYCL 1.2.1 specification. SYCL for OpenCL enables code for heterogeneous processors to be written in a “single-source” style using completely standard modern C++. The multi-vendor SYCL 1.2.1 standard is available royalty-free for industry use, and the full specification together with details about the SYCL open-sourced conformance test suite and Adopters Program are online.

The Khronos™ Group announces the ratification and public release of the finalized SYCL 1.2.1 specification. SYCL for OpenCL enables code for heterogeneous processors to be written in a “single-source” style using completely standard modern C++. The multi-vendor SYCL 1.2.1 standard is available royalty-free for industry use, and the full specification together with details about the SYCL open-sourced conformance test suite and Adopters Program can be found at www.khronos.org/sycl.

Codeplay has set out its intention to lead the development of guidelines to ensure that standards like OpenCL and SYCL meet the strict safety requirements for a range of industries by leading the Khronos SCAP. Illya Rudkin, Principal Software Engineer at Codeplay, is now leading the Khronos Safety Critical Advisory Panel and continues the work done by Erik Noreke to establish the panel. Erik was a long time member of Khronos and well respected for his leadership in numerous working groups. On his appointment Illya said "My role is to continue the work by Erik and grow the participation of both Khronos members and external safety experts within the group. I also hope to enable the group to bring current and new open standards into the safety domain. The demand for safety critical software is growing and we have to ensure adopters of our standards can implement complex systems, often involving multiple layers, as efficiently possible with minimal concerns to safety cases." Learn more about the goals that Illya has for The Safety Critical Advisory Panel. Please contact Khronos if you would like more information about becoming a member, or joining and advisory panel.

Be sure to join AJ Guillon, Yetiware and Yassine Hariri, PhD, CMC Microsystems tomorrow November 8th for the webinar 'Introducing HCMP'. As heterogeneity increases, the gap between the application layer and the hardware layer increased as well. To reduce this gap, we introduce a heterogeneous computing middleware platform (HCMP), which provides middleware that significantly reduces the complexity of developing industrial-strength heterogeneous computing software. Complex tasks such as multi-device memory management, device I/O, kernel scheduling, and dependency management are handled by the platform so that users can focus on writing their applications instead of adhering to complicated specifications.

Join CMC Microsystems and AJ Guillon, chair of the Khronos OpenCL Safety Critical (SC) TSG and founder of YetiWare, on November 8th. This webinar will discuss how to reduce the gap between the application layer and the hardware layer by introducing a heterogeneous computing middleware platform (HCMP), which provides middleware that significantly reduces the complexity of developing industrial-strength heterogeneous computing software using an OpenCL programming model.

Intel to Introduce New CPU-FPGA Hybrid Chip Supported by Acceleration Stack and OpenCLLast year, Intel acquired FPGA-focused Khronos member Altera. Intel has now announced a new line of hybrid chips that combine FPGAs with their well-known CPUs. One of the more interesting aspects of the new Intel FPGA ecosystem is the Acceleration Stack, an OpenCL based programming environment that can be used by developers for hybrid cards or discrete cards, including FPGAs, CPUs, and GPUs. The stack abstracts the programming required for the FPGAs to streamline and speed up development for accelerators and applications being used. Additionally, it allows for code to be reusable — porting between FPGAs/GPU/CPU should be possible without major changes. OpenCL, a C based programming language, will. This is quite the opposite of what had been available when Intel released the E600C seven years ago.

Hybrid CPU-FPGA devices are expected to see widespread adoption. Intel is concentrating on the programming environment so the same tools will be used whether the CPUs and FPGAs are discrete or hybrid in the same socket. This is called the Acceleration Stack for Intel, and it is a complete programming environment that is based on OpenCL, the common higher level programming language that is converged to Verilog and VHDL for FPGAs. Learn more about the roadmap Intel has working on.

ComputeCpp CE for Windows brings SYCL to Windows and Visual StudioCodeplay has announced that ComputeCpp Community Edition is now available on Windows. It is now possible to develop SYCL applications using Windows and Visual Studio. The Windows release of ComputeCpp CE currently supports Windows 7 or 10 and can be used with Visual Studio 2015. Similar to our Linux version, the hardware you want to use with ComputeCpp you is required to have SPIR OpenCL drivers in order to be supported.

IWOCL 2018 - The 6th International Workshop on OpenCLAnnouncing that the 6th International Workshop on OpenCL will take place on the 14-16 May, 2018 at St Catherine's College, Oxford, UK and that the Call for Submissions is now open. Submissions related to any aspect of using OpenCL (including SYCL, Vulkan Compute and OpenCL based libraries) are of interest, including (but not limited to): case-studies of their use in applications, software tools, programming methods, debugging, performance analysis, and integration.

The Xilinx software defined development environment, SDAccel, is now available on Amazon Web Services for use with Amazon Elastic Compute Cloud F1 instances. SDAccel automates the acceleration of software application written in C, C++ or OpenCL by building application-specific FPGA kernels for Amazon EC2 F1.