FPGA tagged news

Altera has published a new whitepaper written by Acceleware, which compares OpenCL programing on GPUs and Altera FPGAs. The paper provides a brief overview of the OpenCL programming model and then focuses on how OpenCL kernels are executed on Altera FPGAs compared to GPUs. The key differences in optimization techniques for targeting FPGAs is also presented.

An informative 25 minute introduction on how to program Altera FPGAs with OpenCL. Presented by Acceleware, the webinar begins with an overview of the OpenCL programming model and data parallelism, before discussing simple OpenCL syntax, kernels and memory spaces. The second part of the webinar examines how OpenCL is mapped to Altera FPGA architecture and how to compile an OpenCL kernel. The presentation concludes with a summary of OpenCL optimizations techniques.

Altera announced that its SDK for OpenCL is conformant to the OpenCL 1.0 standard and is now included on the Khronos Group list of OpenCL conformant products. Altera is the only company to offer an FPGA-optimized OpenCL solution, allowing software developers to harness the massively parallel architecture of an FPGA for system acceleration. Altera will demonstrate its OpenCL solutions at the 2013 Linley Processor Conference, being held October 16-17 in Santa Clara, Calif.

AnandTech takes a look at Altera’s OpenCL SDK for their FPGA. Altera introduced a private beta for OpenCL on FPGAs late last year and the SDK has now been made public. Altera’s implementation is built on top of OpenCL 1.0 but offers custom extensions to tap into the unique features of FPGAs.

FPGA is a large array of fine-grained programmable elements that can be configured in such a way to efficiently solve many complex problems. The primary method of design entry for FPGAs is through Hardware Design Languages (HDLs) such as VHDL or Verilog. This talk by Deshanand Singh of Altera, at the FPL2012 conference, explores techniques o program FPGAs at a level of abstraction that is closer to traditional software-centric approaches using OpenCL.

Altera Corporation today announced its OpenCL for FPGAs Early Access Program (EAP), enabling customers to get a first look at Altera’s OpenCL for FPGA solution. Altera has partnered with Acceleware to offer a course titled “OpenCL for Altera FPGAs” which provides detailed training on the OpenCL language and how to use it with Altera FPGAs. The course is available for OpenCL EAP customers only and will be held in a variety of regions.

Altera Corporation announced that goHDR achieved a significant reduction in development time and a dramatic increase in performance leveraging Altera’s OpenCL for FPGAs. Working closely with Altera, goHDR ported its proprietary C-code to the OpenCL standard and implemented the code in an FPGA in less than a week - a process that typically requires 3-6 months using a traditional HDL flow.