Altera Quartus II Software v14.1 Enables TFLOPS Performance - includes OpenCL

Altera Corporation released its Quartus II software v14.1 featuring expanded support for Arria 10 FPGAs and SoCs, the FPGA industry’s only devices with hardened floating point DSP blocks and the industry’s only 20 nm SoC FPGAs that integrate ARM processors. Altera’s latest software release provides immediate support for the hardened floating point DSP blocks integrated in Arria 10 FPGAs and SoCs. Users can choose between three unique DSP design entry flows and achieve up to an industry-leading 1.5 TFLOPS of DSP performance. These design flows include OpenCL for software programmers, DSP Builder for model-based designers and hardware description language (HDL) flows for traditional FPGA designers.