2016 ISC High Performance

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June 19-23, 2016
AM Main, Frankfurt Germany

In 2016 we offer you another dynamic and power-packed event. We will focus on HPC technological development and its application in scientific fields, as well as its adoption in commercial environments.

OpenCL Schedule

To view a complete list of OpenCL related talks, workshops and BOFs, please visit the event page.

HPC in Asia Poster Session

Date: Wednesday, June 22, 2016 Time: 10:00 am - 11:00 am
Location: Analog 1+2, Messe Frankfurt

  • (A01) Capability Assessment of a Multiple-FPGA System for High-Performance Computing
    Iman Firmansyah, University of Tsukuba
  • (A02) Automated High-Performance Computing Cluster System for a Bioinformatics Application in a Cloud Environment
    Iksu Byeon, KRIBB
  • (A03) SCAMP: A “Pseudo” Trace Driven Simulation toward Scalable Network Evaluation
    Miwako Tsuji, RIKEN/AICS
  • (A04) Block Time Step Storage Scheme for Astrophysical N-Body Simulations
    Maxwell Xu Cai, CAS
  • (A05) Auto-Tuning of OpenACC Using ppOpen-AT
    Satoshi Ohshima, University of Tokyo
  • (A06) Electron Dynamics Simulation with Time-Dependent Density Functional Theory on Large Scale Knights-Corner Cluster
    Yuta Hirokawa, University of Tsukuba
  • (A07) XMP-Tasklet: Multitasking in a PGAS Language for Many-Core Clusters
    Jinpil Lee, RIKEN/AICS
  • (A08) MYX: MUST Correctness Checking for YML & XMP Programs
    Hitoshi Murai, RIKEN/AICS
  • (A09) Implementation & Performance Evaluation of NAS Parallel CG Benchmark on GPU Cluster with Proprietary Interconnect TCA
    Norihisa Fujita, University of Tsukuba
  • (A10) Performance Evaluation of Low-Latency Inter-Node Communication between GPUs Using PEACH3
    Toshihiro Hanawa, University of Tokyo
  • (A11) HPC in Asia Award Winning Poster: Performance of Quadruple Precision Eigenvalue Solver Libraries QPEigenK & QPEigenG on the K Computer
    Yusuke Hirota, RIKEN/AICS
  • (A12) Acceleration of a Compressed Flow Analysis Application with OpenACC
    Tetsuya Hoshino, University of Tokyo
  • (A13) Exception Handling with Collateral Task Abortion in Distributed Memory Environments
    Tasuku Hiraishi, Kyoto University
  • (A14) HCA Aware Parallel Communication Library: A Feasibility Study for Offloading MPI
    Kedar R. Kulkarni, C-DAC
  • (A15) Simplifying the Access to HPC Resources by Integrating them in the Application GUI
    Matthijs van Waveren, KAUST

First International Workshop on Performance Portable Programming Models for Accelerators

Date: Thursday, June 23, 2016 Time: 09:00 am - 06:00 pm
Location: Alabaster 1, Frankfurt Marriott Hotel
Organizer: Sunita Chandrasekaran, University of Delaware, Graham Lopez, ORNL
Targeted Audience: Scientists, Compiler and Tools Developers, Researchers and Vendors in the area of HPC
Workshop URL: http://www.csm.ornl.gov/workshops/p3ma2016/

Abstract: High-Level programming models offer scientific applications a path onto HPC platforms without an undue loss of portability or programmer productivity. For example, using directives, application developers can port their codes to accelerators incrementally while minimizing code changes. Other approaches include Domain Specific Languages, C++ metaprogramming, and runtimes APIs being developed for Exascale which are starting to emerge. Although these approaches aim to introduce abstraction without performance penalty, programming challenges are still manyfold especially with their designs, implementations and application porting experiences on rapidly evolving hardware, some with diverse memory subsystems. The programming approaches will need to adapt to such developments and make improvements to raise their performance portability that will increase the productivity of accelerators as HPC components. Such improvements are continuously being discussed with standards committees for C++, OpenCL, OpenMP, OpenACC, and Exascale co-design centers for DSLs. This workshop is designed to assess the improved features of programming models (including but not limited to directives-based programming models), their implementations, and experiences with their deployment in HPC applications. The workshop will provide a forum for bringing together researchers, vendors, users and developers to brainstorm aspects of heterogeneous computing and its various tools and techniques.

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