Neuro-Systems Emulsion is a photorealistic rendering studio using OpenCL for realtime and non-realtime physically-based techniques that can transform brute 3D models into photorealistic images, adjusted in real time. Emulsion can easily integrate these projects directly into a video source or digital pictures using photorealistic augmented reality.
The 10th HiPEAC conference will take place in Amsterdam, The Netherlands from Monday, January 19 to Wednesday, January 21, 2015. HiPEAC is an academic oriented, 3-day, international conference around HPC, compilers and processors. Associated workshops, tutorials, special sessions, several large poster session and an industrial exhibition will run in parallel with the conference.
The call for submissions for the 3rd IWOCL is now open, seeking research papers, technical presentations, workshops, tutorials and posters from industry and academia. Submissions may relate directly to the use of OpenCL, SYCL or SPIR as well as libraries, toolkits and programming techniques based on OpenCL. Submissions may refer to both completed projects or those currently in progress. Submission deadline: 14th February 2015.
Xilinx, Inc. announced that the SDAccel development environment for OpenCL, C, and C++ is now Khronos OpenCL 1.0 standard compliant. The OpenCL standard provides a uniform programming environment for software developers to write efficient, portable code enabling a rich range of algorithms to be easily accelerated on Xilinx FPGAs. SDAccel, the newest member of the SDx family, includes an architecturally optimizing compiler for OpenCL, C, and C++ and is proven to deliver up to 25X better performance/watt compared to CPUs or GPUs and 3X the performance and resource efficiency of other FPGA solutions.
After four pre-releases, the stable 2.0.0 version of cf4ocl, the C Framework for OpenCL, is now available. Since the last beta release, a number of tests were added, and a few bug fixes have been fixed. Support for device fission and native kernels has also been implemented. A complete list of features and fixes is available online. Cf4ocl has been tested on Linux, OS X and Windows, and offers a pure C object-oriented framework for developing and benchmarking OpenCL projects in C.
AMD's first high-performance system-on-a-chip (SoC) and next-generation Mobile APU codenamed "Carrizo" showcased at CES 2015. Expected in market by mid-year, "Carrizo" will arrive with support for next-generation APIs such as DirectX 12 and OpenCL 2.0.
OmniVision Technologies announced the availability of an OpenCL optimized imaging algorithm library ideally suited for ARM Mali GPUs. The library includes advanced imaging features such as 3D noise suppression, chroma noise reduction, de-fringe and de-haze and is targeted at smartphones, tablets and notebooks.
Come to the SYCL @ CGO Tutorial on the afternoon of Saturday, February the 7th 2015 (2/7/2015); as part of The 2015 International Symposium on Code Generation and Optimization (CGO) at the San Francisco Airport Marriott Waterfront Hotel. This tutorial will include "An introduction to SYCL for OpenCL" (with Lee Howes, Qualcomm); "triSYCL: experiments around SYCL with an open-source implementation" (with Ronan Keryell, AMD); and "Working with SYCL on OpenCL devices" (with Ruyman Reyes, Codeplay). Sign up for the SYCL @ CGO Tutorial in addition to registration for the CGO Conference; or as a standalone workshop/tutorial-only registration. Please note that early bird registration must be completed by Jan 11, 2015.
An open source two-day lecture course for teaching and learning OpenCL has now been downloaded over 3000 times. This KITE initiative carried out by Simon McIntosh-Smith and Tom Deakin from the University of Bristol in the UK is expecting a small update in the new year, when some more advanced material on code optimisation will be added. Simon said "I would have expected hundreds, and anything over 1,000 would have been awesome. But 3,000!!! I am stunned."
Altera Corporation released its Quartus II software v14.1 featuring expanded support for Arria 10 FPGAs and SoCs, the FPGA industry's only devices with hardened floating point DSP blocks and the industry's only 20 nm SoC FPGAs that integrate ARM processors. Altera's latest software release provides immediate support for the hardened floating point DSP blocks integrated in Arria 10 FPGAs and SoCs. Users can choose between three unique DSP design entry flows and achieve up to an industry-leading 1.5 TFLOPS of DSP performance. These design flows include OpenCL for software programmers, DSP Builder for model-based designers and hardware description language (HDL) flows for traditional FPGA designers.