Supercomputing is underway in Denver, Colorado! The 30th annual conference is this week from November 13 through 16, and explores high-performance computing, networking, storage, and analysis. Khronos will be at the show (Booth #394) to demonstrate how Khronos standards, especially SYCL, are playing their parts in HPC today. In addition to in-booth demos and presentations from Khronos members Codeplay and Xilinx, Khronos is giving away HPC t-shirts as well as SYCL and OpenCL stickers and reference guides at the booth.
Intel has announced the availability of a new Graphics driver, namely version 220.127.116.1149, which adds support for Microsoft Windows 10 Fall Creators update features. This update also resolves the intermittent crashes/hangs encountered in DOTA 2 (Vulkan version), enhances memory usage in OpenCL applications.
Be sure to join AJ Guillon, Yetiware and Yassine Hariri, PhD, CMC Microsystems tomorrow November 8th for the webinar 'Introducing HCMP'. As heterogeneity increases, the gap between the application layer and the hardware layer increased as well. To reduce this gap, we introduce a heterogeneous computing middleware platform (HCMP), which provides middleware that significantly reduces the complexity of developing industrial-strength heterogeneous computing software. Complex tasks such as multi-device memory management, device I/O, kernel scheduling, and dependency management are handled by the platform so that users can focus on writing their applications instead of adhering to complicated specifications.
Join CMC Microsystems and AJ Guillon, chair of the Khronos OpenCL Safety Critical (SC) TSG and founder of YetiWare, on November 8th. This webinar will discuss how to reduce the gap between the application layer and the hardware layer by introducing a heterogeneous computing middleware platform (HCMP), which provides middleware that significantly reduces the complexity of developing industrial-strength heterogeneous computing software using an OpenCL programming model.
Last year, Intel acquired FPGA-focused Khronos member Altera. Intel has now announced a new line of hybrid chips that combine FPGAs with their well-known CPUs. One of the more interesting aspects of the new Intel FPGA ecosystem is the Acceleration Stack, an OpenCL based programming environment that can be used by developers for hybrid cards or discrete cards, including FPGAs, CPUs, and GPUs. The stack abstracts the programming required for the FPGAs to streamline and speed up development for accelerators and applications being used. Additionally, it allows for code to be reusable — porting between FPGAs/GPU/CPU should be possible without major changes. OpenCL, a C based programming language, will. This is quite the opposite of what had been available when Intel released the E600C seven years ago.
Hybrid CPU-FPGA devices are expected to see widespread adoption. Intel is concentrating on the programming environment so the same tools will be used whether the CPUs and FPGAs are discrete or hybrid in the same socket. This is called the Acceleration Stack for Intel, and it is a complete programming environment that is based on OpenCL, the common higher level programming language that is converged to Verilog and VHDL for FPGAs. Learn more about the roadmap Intel has working on.
Announcing that the 6th International Workshop on OpenCL will take place on the 14-16 May, 2018 at St Catherine's College, Oxford, UK and that the Call for Submissions is now open. Submissions related to any aspect of using OpenCL (including SYCL, Vulkan Compute and OpenCL based libraries) are of interest, including (but not limited to): case-studies of their use in applications, software tools, programming methods, debugging, performance analysis, and integration.
The Xilinx software defined development environment, SDAccel, is now available on Amazon Web Services for use with Amazon Elastic Compute Cloud F1 instances. SDAccel automates the acceleration of software application written in C, C++ or OpenCL by building application-specific FPGA kernels for Amazon EC2 F1.