Synopsys, Inc announced availability of its new ASIP Designer tool that speeds the design of application-specific instruction-set processors (ASIPs) and programmable accelerators. Integrated LLVM-based compiler front-end and OpenCL kernel language support enables efficient compilation of C, C++ and OpenCL-based application code.
The new AIDA64 release implements optimized benchmarks for AMD “Carrizo” and Intel “Broadwell” processors, SensorPanel and external LCD improvements, and supports the latest nVIDIA GeForce and Quadro graphics accelerators, including OpenCL 2.1 support.
Neil Trevett, Khronos Group President, spoke at the recent GPU Technology Conference on Vulkan, SPIR-V and OpenCL 2.1 as well as at the WebGL Meetup on Building Standards. Both presentations are now available online.
Voices of VR has three new podcasts featuring Neil Trevett, President of the Khronos Group. The podcasts include an overview of the Khronos Group, the new Vulkan API, OpenCL 2.1 and SPIR-V.
The Khronos group has uploaded slide decks from the Vulkan and OpenCL presentations at GDC. The original press briefing slide deck is included. The slides cover SPIR-V as well and can also be seen in the online video from the March 5th Vulkan session.
Please join us at 2PM pacific time for a Live Stream of the second and last Vulkan session at GDC. There will be better quality video and slides available in the next few days.
G-Truc Creation has posted an excellent and well balanced overview of SPIR-V – The first open standard intermediate language for parallel compute and graphics. "I am looking forward to the shading language revolution that SPIR-V will lead to, one step at a time!" sums up Christophe Riccio.
The Khronos Group today announced the ratification and public release of the OpenCL 2.1 provisional specification. OpenCL 2.1 is a significant evolution of the open, royalty-free standard for heterogeneous parallel programming that defines a new kernel language based on a subset of C++ for significantly enhanced programmer productivity, and support for the new Khronos SPIR-V cross-API shader program intermediate language now used by both OpenCL and the new Vulkan graphics API.
Press Release: Khronos Releases OpenCL 2.1 Provisional Specification for Public Review
Video of Live OpenCL Session
OpenCL Feedback thread: We look forward to hearing from you.
Overview slide: Powerpoint presentation outlining OpenCL 2.1
Khronos Releases SPIR-V The first open standard intermediate language for parallel compute and graphics
In another significant announcement today, OpenCL 2.1 and Vulkan™, the new open standard API for high-efficiency access to graphics and compute on modern GPUs, are now sharing core intermediate language technologies resulting in SPIR-V; a revolution in the Khronos Standard Portable Intermediate Representation initially used by OpenCL™, now fully defined by Khronos with native support for shader and kernel features. SPIR-V splits the compiler chain, enabling high-level language front-ends to emit programs in a standardized intermediate form to be ingested by Vulkan or OpenCL drivers. Eliminating the need for a built-in high-level language source compiler significantly reduces driver complexity and will enable a diversity of language front-ends. Additionally, a standardized IR provides a measure of kernel IP protection, accelerated kernel load times and enables developers to use a common language front-end, improving kernel reliability and portability across multiple implementations. You can read more on the SPIR homepage, registry and whitepaper, and give us valuable community feedback in our SPIR forum.
Microsoft achieves compelling Performance-per-Watt in cloud data center acceleration with OpenCL powered FPGAs
Altera Corporation announced Microsoft is using Altera Arria 10 FPGAs to achieve compelling performance-per-Watt in data center acceleration based on CNN (convolutional neural network) algorithms. This performance is achieved using the open software development language known as OpenCL, or VHDL to code the Arria 10 FPGA and its IEEE754 hard floating point DSP (digital signal processing) blocks.