Skip to main content

Supercomputing 2023
Supercomputing 2023 Banner
November 12-15, 2023
Denver, CO. USA

i am hpc!

The International Conference for High Performance Computing, Networking, Storage, and Analysis

Khronos Related Sessions

Hands-On HPC Application Development Using C++ and SYCL

SC 23 Listing
Date: Monday, 13 November, 8:30am - 5pm MST
Location: 403
Speakers: Rod Burns, Codeplay Software; Michael Wong, Codeplay Software; James Reinders, Intel; Ronan Keryell, AMD; Thomas Applenourt, Argonne National Laboratory; Phuong Nguyen, Univeristy of Tennessee
Description: SYCL is a programming model that lets developers support a wide variety of devices (CPUs, GPUs, and more) from a single code base. Given the growing heterogeneity of processor roadmaps, moving to an open standard, platform-independent model such as SYCL is essential for modern software developers. SYCL has the further advantage of supporting a single-source style of programming from completely standard C++.

In this tutorial, we will introduce SYCL and provide programmers with a solid foundation they can build on to gain mastery of this language. The main benefit of using SYCL over other heterogeneous programming models is the single programming language approach, which enables one to target multiple devices using the same programming model, and therefore to have a cleaner, portable, and more readable code.

This is a hands-on tutorial. The real learning will happen as students write code. The format will be short presentations followed by hands-on exercises. Hence, attendees will require their own laptop to perform the hands-on exercises.

Tenth Workshop on Accelerator Programming Using Directives

SC 23 Listing
Date: Monday, 13 November, 9am - 12:30pm MST
Location: 507
Speakers: Maciej Cytowski, Pawsey Supercomputing Research Centre; Jose M. Monsalve Diaz, Argonne National Laboratory; Verónica G. Melesse Vergara, Oark Ridge National Laboratory
Description: Heterogeneous node architectures are becoming omnipresent in today’s HPC systems. Exploiting the maximum compute capability out of such systems, while also maintaining code portability and
maintainability, necessitates accelerator programming approaches such as OpenMP offloading, OpenACC, standard C++/Fortran parallelism, SYCL, DPC++, Kokkos, RAJA. However, the use of these programming approaches remains a research activity and there are many possible trade-offs between performance, portability, maintainability, and ease of use that must be considered for optimal use of accelerator-based HPC systems.

Toward this end, the workshop will highlight the improvements over state-of-the-art through the accepted papers and talks. In addition, the event will foster discussion with a keynote/panel to draw the community’s attention to key areas that will facilitate the transition to accelerator-based HPC. The workshop aims to showcase all aspects of innovative high-level language features, lessons learned while using directives/abstractions to migrate scientific legacy code, experiences using novel accelerator architectures, among others.

Khronos SYCL: What's Next?

SC 23 Listing
When: Tuesday, 14 November, 5:15pm - 6:45pm MST
Location: 601-603
Session Leaders: Tom Deakin, University of Bristol; James Brodman, Intel; Michael Wong, Codeplay Software
Description: The SYCL programming model provides an open standard way to program heterogeneous systems in modern C++. Since the major SYCL2020 release, which added abstractions and features for HPC, SYCL has seen increased use in application domains needing large Exascale-class machines, including fusion energy, molecular dynamics, and aerospace.

In this Birds of a Feather, we will bring together the community of everyone using and developing SYCL applications and implementations. We will discuss future directions and seek feedback on priorities for SYCLNext. A panel of SYCL experts, runtime/compiler implementers, and application specialists, will lead an audience discussion and Q&A.

Portable and Scalable All-Electron Quantum Perturbation Simulations on Exascale Supercomputers

SC 23 Listing
Date: Wednesday, 15 November, 10:30am - 11am MST
Location: 301-302-303
Speakers: Zhikun Wu, Institute of Computing Technology; Yangjun Wu, Institute of Computing Technology; Ying Liu, Institute of Computing Technology; Honhui Shang, University of Science and Technology of China; Yingxiang Gao, National Supercomputer Center in Tianjin; Zhongcheng Zhang, Institute of Computing Technology; Yuyang Zhang, Institute of Computing Technology; Yingchi Long, Institute of Computing Technology; Xiaobing Feng, Institute of Computing Technology; Huiming Cui, Institute of Computing Technology
Description: Quantum perturbation theory is pivotal in determining the critical physical properties of materials. The first-principles computations of these properties have yielded profound and quantitative insights in diverse domains of chemistry and physics.

In this work, we propose a portable and scalable OpenCL implementation for quantum perturbation theory, which can be generalized across various high-performance computing (HPC) systems. Optimal portability is realized through the utilization of a cross-platform unified interface and a collection of performance-portable heterogeneous optimizations. Exceptional scalability is attained by addressing major constraints on memory and communication, employing a locality-enhanced task mapping strategy and a packed hierarchical collective communication scheme. Experiments on two advanced supercomputers demonstrate that the quantum perturbation calculation exhibits remarkably performance on various material systems, scaling the system to 200,000 atoms with all-electron precision. This research enables all-electron quantum perturbation simulations on substantially larger molecular scales, with a potentially significant impact on progress in material sciences.

SYnergy: Fine-Grained Energy-Efficient Heterogeneous Computing for Scalable Energy Saving

SC 23 Listing
Date: Wednesday, 15 November, 4:30pm - 5pm MST
Location: 405-406-407
Speakers: Kaijie Fan, TU Berlin; Marco D'antonio, University of Salerno; Lorenzo Carpentieri, University of Salerno; Biagio Cosenza, University of Salerno; Dederico Ficarelli, CINECA; Daniele Cesarini, CINECA
Description: Energy-efficient computing uses power management techniques such as frequency scaling to save energy. Implementing energy-efficient techniques on large-scale computing systems is challenging. While most modern architectures, including GPUs, are capable of frequency scaling, these features are often not available on large systems.

We propose SYnergy, a novel energy-efficient approach that spans languages, compilers, runtimes, and job schedulers to achieve unprecedented fine-grained energy savings on large-scale heterogeneous clusters. SYnergy defines an extension to the SYCL programming model that allows programmers to define a specific energy goal for each kernel. Through compiler integration and a machine learning model, each kernel is statically optimized for the specific target. The methodology is inherently portable and has been evaluated on both NVIDIA and AMD GPUs. Experimental results show unprecedented improvements in energy and energy-related metrics on real-world applications, as well as scalable energy savings on a 64-GPU cluster.

Ninth International Workshop on Heterogeneous High-Performance Reconfigurable Computing

SC 23 Listing
Date: Friday, 17 November, 8:30am - 12pm MST
Location: 301-302-303
Speakers: Kenneth O'Brien, AMD; Jason Bakos, University of South Carolina; Christian Plessl, Paderborn University; Torsten Hoefler, ETH Zurich; Franck Cappello, Argonne National Laboratory
Description: As in the previous eight years, this workshop will bring together application experts, software developers, and hardware engineers, both from industry and academia, to share experiences and best practices to leverage the practical application of reconfigurable logic to Scientific Computing, Machine/Deep Learning, and “Big Data” applications. In particular, the workshop will focus on sharing experiences and techniques for accelerating applications and/or improving energy efficiency with FPGAs using OpenCL, OpenMP, OpenACC, SYCL, DPC++, C, C++, and other high-level design flows, which enable and improve cross-platform functional and performance portability while also improving productivity. Particular emphasis is given to cross-platform comparisons and combinations that foster a better understanding within the industry and research community on what are the best mappings of applications to a diverse range of hardware architectures that are available today (e.g., FPGA, GPU, Many-cores and hybrid devices, ASICs), and on how to most effectively achieve cross-platform compatibility.

Khronos videos, presentations, and upcoming events. Skip to the Footer