Skip to main content

SC22
SC22 Banner
November 13-18, 2022
Kay Bailey Hutchison Convention Center, Dallas, Texas

The SC Conference extends a warm welcome to our first-time attendees! SC started in 1988, and since then we’ve grown to host over 13,000 individuals at our events.

Why Attend SC?

SC is one of the largest HPC conferences in the world. We host thousands of students, exhibitors, and presenters representing institutions of every shape and size. Our volunteers are committed to bring you a broad range of experiences to help you get the most out of the event. In fact, here below is what a few of our leaders have to say about their own first time at SC.

Register

Khronos Related Sessions

Towards Cross-Platform Portability of Coupled-Cluster Methods with Perturbative Triples using SYCL

Presenters: Abhishek Bagusetty, Ajay Panyala, Gordon Brown, Jack Kirk
Time: Sunday, 13 November 2022, 1:09pm - 1:31pm CST
Location: C155
Description: Tensor contractions form the fundamental computational operation of computational chemistry and more notably, these contractions dictate the performance of widely used coupled-cluster (CC) methods in computational chemistry. In this work, we study a single-source, cross-platform C++ abstraction layer programming model, SYCL for the application related to the computational chemistry methods such as CCSD(T) coupled-cluster formalism. An existing optimized CUDA implementation was migrated to SYCL to make use of the novel algorithm that provides tractable GPU memory needs for solving high-dimensional tensor contractions for accelerating CCSD(T). We present the cross-platform performance achieved using SYCL implementations for the non-iterative triples contribution of CCSD(T) formalism which is considered as the performance bottle neck on Nvidia A100 and AMD Instinct MI250X. Additionally, we also draw comparisons of similar performance metrics from vendor-based native programming models such as CUDA and ROCm HIP.

Evaluating Nonuniform Reduction in HIP and SYCL on GPUs

Presenters: Zheming Jin, Jeffrey Vetter
Time: Sunday, 13 November 2022, 1:30pm - 2pm CST
Location: C141
Description: Motivated by promising programming models and portability for heterogeneous computing, we describe the challenges posed by hardware architectures and programming models when migrating a highly optimized implementation of nonuniform reduction from CUDA to HIP and SYCL. We explain the migration experience, evaluate the performance of the reduction on an NVIDIA V100 GPU and an AMD MI100 GPU, and provide feedback on improving portability for the development of the SYCL programming model.

Toward Performance Portability of AI Graphs Using SYCL

Presenters: Kumudha Narasimhan, Ouadie El Farouki, Mehdi Goli, Muhammad Tanvir, Svetlozar Georgiev, Isaac Ault
Time: Sunday, 13 November 2022, 2:46pm - 3:09pm CST
Location: C155
Description: The wide adoption of Deep Neural Networks (DNN) has served as an incentive to design and manufacture powerful and specialized hardware technologies, targeting systems from Edge devices to Cloud and supercomputers.

While the proposed ONNX as a de facto for AI model description provides the portability of AI models across various AI frameworks, supporting DNN models on various hardware architectures remains challenging.

SYCL provides a C++-based portable parallel programming model to target various devices. Thus, enabling SYCL backend for an AI framework can lead to a hardware-agnostic model for heterogeneous systems.

This paper proposes a SYCL backend for ONNXRuntime as a possible solution towards the performance portability of deep learning algorithms. The proposed backend uses existing state-of-the-art SYCL-DNN and SYCL-BLAS libraries to invoke tuned SYCL kernels for DNN operations. Our performance evaluation shows that the proposed approach can achieve comparable performance with respect to the state-of-the-art optimized vendor-specific libraries.

Tutorial: Hands-On HPC Application Development Using C++ and SYCL

Presenters: Rod Burns, Dounia Khaldi, Michael Wong, James Reinders, Ronan Keryell
Time: Monday, 14 November 2022, 8:30am - 5pm CST
Location: D173
Description: SYCL is a programming model that lets developers support a wide variety of devices (CPUs, GPUs, and more) from a single code base. Given the growing heterogeneity of processor roadmaps, moving to an open standard, platform-independent model such as SYCL is essential for modern software developers. SYCL has the further advantage of supporting a single-source style of programming from completely standard C++.

In this tutorial, we will introduce SYCL and provide programmers with a solid foundation they can build on to gain mastery of this language. The main benefit of using SYCL over other heterogeneous programming models is the single programming language approach, which enables one to target multiple devices using the same programming model, and therefore to have a cleaner, portable, and more readable code.

This is a hands-on tutorial. The real learning will happen as students write code. The format will be short presentations followed by hands-on exercises. Hence, attendees will require their own laptop to perform the hands-on exercises.

A First Step towards Support for MPI Partitioned Communication on SYCL-programmed FPGAs

Presenters: Steffen Christgau, Marius Knaust, Thomas Steink
Time: Monday, 14 November 2022, 10:30am - 11:00am CST
Location: C146
Description: Version 4.0 of the Message Passing Interface standard introduced the concept of Partitioned Communication which adds support for multiple contributions to a communication buffer. Although initially targeted at multithreaded MPI applications, Partitioned Communication currently receives attraction in the context of accelerators, especially GPUs. In this publication it is demonstrated that this communication concept can also be implemented for SYCL-programmed FPGAs. This includes a discussion of the design space and the presentation of a prototypical implementation. Experimental results show that a lightweight implementation on top of an existing MPI library is possible. In addition, the presented approach also reveals issues in both the SYCL and the MPI standard which need the addresses for improved support for the intended communication style.

Evaluating ISO C++ Parallel Algorithms on Heterogeneous HPC Systems

Presenters: Wei-Chen Lin, Tom Deakin, Simon McIntosh-Smith
Time: Monday, 14 November 2022, 11:00am - 11:30am CST
Location: C155
Description:

Recent revisions to the ISO C++ standard have added specifications for parallel algorithms. These additions cover common use-cases, including sequence traversal, reduction, and even sorting, many of which are highly applicable in HPC, and thus represent a potential for increased performance and productivity.

This study evaluates the state of the art for implementing heterogeneous HPC applications using the latest built-in ISO C++17 parallel algorithms. We implement C++17 ports of representative HPC mini-apps that cover both compute-bound and memory bandwidth-bound applications. We then conduct benchmarks on CPUs and GPUs, comparing our ports to other widely-available parallel programming models, such as OpenMP, CUDA, and SYCL.

Finally, we show that C++17 parallel algorithms are able to achieve competitive performance across multiple mini-apps on many platforms, with some notable exceptions. We also discuss several key topics, including productivity, and describe workarounds for a number of remaining issues, including index-based traversal and accelerator device/memory management.

BOF: Khronos SYCL - Current and Future Directions

Presenters: Tom Deakin, Michael Wong, James Brodman
Time: Tuesday, 15 November 2022, 5:15pm - 6:45pm CST
Location: C155-156
Description: SYCL is an open standard with a new release in 2020. After SC17, SC18, SC19, and SC20, SC21’s successful ISO C++ SYCL BoF, and with increasing use of C++ in HPC, there was popular demand for updates on the new SYCL 2020 features and current developments. It means developers will be able to write their HPC software using the SYCL standard and that will enable the same software on the forthcoming Aurora supercomputer at Argonne National Lab, NERSC, LBL, ORNL, and potentially, supercomputers with other architectures, including AMD, ARM, or RISC-V.

SYCL Portability: Tips and Tricks for Porting High Performance Libraries and Applications

Presenters: Noah Clemons, Hartwig Anzt, Yu-Hsiang Mike Tsai
Time: Wednesday, 16 November 2022, 12:15pm - 1:15pm CST
Location: D171
Description: SYCL is a powerful way to enable multi-vendor support for high performance libraries, languages, and packages, while still allowing the originally desired programmer productivity and performance. While many BoFs/Presentations will focus on the end results of a port, this BoF is meant to share lessons learned in porting a diverse array of previously vendor-specific implementations to SYCL, how they enforced numerical reproducibility, and then added flexible vectorization for portable performance. This BoF will place strong emphasis on sharing cross architecture debugging techniques.

Panel: Runtimes Systems for Extreme Heterogeneity: Challenges and Opportunities

Moderators: Pedro Valero-Lara, Jeffrey Vetter
Panelists: Michael Wong, Johannes Doerfert, Rosa Badia, George Bosilca, Olivier Aumage, Sunita Chandrasekaran, Jesus Labarta
Time: Wednesday, 16 November 2022, 1:30pm - 3pm CST
Location: C155-156
Description: The goal of this panel is to discuss the latest runtime evolution and the impact on applications. Advances in this matter are key to executing science workflows and understanding their results, enabling efficient execution on diverse platforms, ensuring scalability of high-level descriptions of analytics workflows, and increasing user productivity and system utilization. In other words, how easily and rapidly a science team can develop or port a workflow to a new platform, and how well the resulting implementation makes use of the platform and its resources.

Our panel includes a large number of different runtimes. Examples of these are OpenMP, OpenACC, SYCL, COMPS, PaRSEC, OmpSs, and StarPU. This is a great opportunity to bring together some of the most important and widely used runtimes and programming models, and present/discuss the latest efforts on each of them and the different perspectives to face the challenges of the upcoming extreme heterogeneity era.

Ninth Workshop on Accelerator Programming Using Directives (WACCPD 2022)

Organizers: Christopher Daley, Jose M. Monsalve Diaz, Veronica G. Melesse Vergara
Time: Friday, 18 November 2022, 8:30am - 12pm CST
Location: D174
Description: Heterogeneous node architectures are becoming omnipresent in today’s HPC systems. Exploiting the maximum compute capability out of such systems, while also maintaining code portability and maintainability, necessitates accelerator programming approaches such as OpenMP offloading, OpenACC, standard C++/Fortran parallelism, SYCL, DPC++, Kokkos, and RAJA. However, the use of these programming approaches remains a research activity and there are many possible trade-offs between performance, portability, maintainability, and ease of use that must be considered for optimal use of accelerator-based HPC systems.

Toward this end, the workshop will highlight the improvements over state-of-the-art through the accepted papers. In addition, the event will foster discussion with a keynote/panel to draw the community’s attention to key areas that will facilitate the transition to accelerator-based HPC. The workshop aims to showcase all aspects of innovative high-level language features, lessons learned while using directives/abstractions to migrate scientific legacy code, experiences using novel accelerator architectures, among others.

Panel: The oneAPI Software Abstraction for Heterogeneous Computing

Moderator: Henry Gabb
Panelists: James Reinders, Aksel Alpay, Kumudha Narasimhan, Ronan Keryell, Zheming Jin
Time: Friday, 18 November 2022, 10:30am - 12pm CST
Location: C155-156
Description: oneAPI is a cross-industry, open, standards-based unified programming model. The oneAPI specification extends existing developer programming models to enable a diverse set of hardware through language, a set of library APIs, and a low-level hardware interface to support cross-architecture programming. It builds upon industry standards and provides an open, cross-platform developer stack to improve productivity and innovation. At the core of oneAPI is the SYCL programming language developed by the Khronos Group, which builds on the ISO C++ standard. SYCL provides explicit parallel constructs and offload interfaces to support a broad range of accelerators. In addition to direct accelerator programming with SYCL, oneAPI also provides libraries for compute- and data-intensive domains, e.g.: deep learning, scientific computing, video analytics, and media processing. Finally, a low-level hardware interface defines a set of capabilities and services to allow a language runtime system to effectively utilize a hardware accelerator.

Khronos videos, presentations, and upcoming events. Skip to the Footer