Heterogeneous computing is everywhere you look, and the push to focus on open standards continues. We will have an OpenCL booth this year, as well as our most exciting and comprehensive BOF ever.
Bookmark this web page as your information hub to everything Khronos at SC’15.
OpenCL Booth: #285
Stop by for a chat and a free reference guide
Visit us on the west side of the hall in booth #285. We’ll have technical experts available to answer your questions. There will be OpenCL 2.1 and SYCL reference guides to give away. We also have a handy flyer that you pickup at our booth or download and print in PDF format.
Meet some of the OpenCL, SPIR, and SYCL workgroup members
Learn about the NEW OpenCL 2.1
Get your free OpenCL, SYCL, and SPIR stickers
Free reference guides for OpenCL 2.1 and SYCL 1.2
Flocking Together: Experience the Diverse OpenCL Ecosystem
Date & Time: Wednesday, November 18, at 5:30pm–7pm Room: 17AB Session Leaders: Simon McIntosh-Smith (University of Bristol), Tim Mattson (Intel Corporation) Event Page
Here's who we have lined up to join us in our BOF:
Just as birds of a feather flock together, the strength of OpenCL is in how it was created and maintained by a consortium of like-minded organizations. This has resulted in its acceptance and implementations across the ecosystem, making it a highly portable, non-proprietary HPC option.
We will start our BOF with an overview of the OpenCL 2.1 C++ kernel language, the SYCL 2.1 abstraction layer, and SPIR.
Following this presentation, We invite attendees to bring their code and their toughest questions and join the OpenCL petting zoo. You will have the opportunity to experiment with implementations and tools from multiple vendors across several platforms.
While this session is geared for those experienced with OpenCL, it will also provide an opportunity for newcomers to ask questions both basic and technical of our experts from the OpenCL working group as well as those from various participating vendors, including Altera, Xilinx, AMD, Intel, and more.
Courses, Papers & BOFs @ SC’2015
Workshop: First International Workshop on Heterogeneous Computing With Reconfigurable Logic
Date & Time: Sunday, November 15, 9:00AM - 12:30PM Room: Salon D | Event page Organizers: Kevin Skadron, Torsten Hoefler, Michael Lysaght, Jason Bakos, Michaela Blott
The advent of high-level synthesis (HLS) creates exciting new opportunities for using FPGAs in HPC. HLS allows programs written in OpenCL, C, etc. to be mapped directly and effectively to FPGAs, without the need for low-level RTL design. At the same time, FPGA-based acceleration presents the opportunity for dramatic improvements in performance and energy-efficiency for a variety of HPC applications. This workshop will bring together application experts, FPGA experts, and researchers in heterogeneous computing to present cutting-edge research and explore opportunities and needs for future research in this area.
More at: http://h2rc.cse.sc.edu/
Tutorial: Portable programs for heterogeneous computing: a hands-on introduction
Date & Time: Monday, November 16, 8:30AM - 5:00PM Room: 17B | Event page Presenters: Tim Mattson (Intel Corporation), Alice Koniges, Simon McIntosh-Smith (University of Bristol)
Heterogeneous computing involves programs running on systems composed of some combination of CPUs, GPUs and other processors critical for high performance computing (HPC). To succeed as a long-term architecture for HPC, however, it is vital that the center of attention shift away from proprietary programming models to standards-based approaches.
This tutorial is a unique blend of a high-level survey and a hands-on introduction to writing portable software for heterogeneous platforms. We will only work with portable APIs and languages supported by vendor-neutral standards. We believe such an approach is critical if the goal is to build a body of software for use across multiple hardware generations and platforms from competing vendors.
We’ll start with OpenCL using the Python interface. By using Python we avoid many of the complexities associated with the host programming API thereby freeing-up more time to focus on the kernel programs that run on the OpenCL devices (such as a GPU or the Intel® Xeon Phi™ coprocessor). Then in the second half of the tutorial, we will shift gears to the OpenMP 4.1 target directive (and associated constructs).
Poster: FPGA based OpenCL acceleration of genome sequencing software
Date & Time: Tuesday, November 17, 5:15PM - 7:00PM Room: Level 4 – Lobby | Poster page Session Chairs: Michela Becchi, Manish Parashar, Dorian C. Arnold Authors: Ashish Sirasao, Elliott Delaye, Ravi Sunkavalli, Stephen Neuendorffer all from Xilinx
The Smith-Waterman algorithm produces the optimal pairwise alignment between two sequences of proteins or nucleotides and is frequently used as a key component of alignment and variation detection tools for next-generation sequencing data. In this paper an efficient and scalable implementation of the Smith-Waterman algorithm is written in OpenCL and implemented on a Xilinx Virtex-7 FPGA which shows >2x compute performance and 18x-20x performance per watt advantage compared with 12 core and 60 core CPUs. Against a GPU we show a 30% performance advantage and 11.6x better performance per watt. These results were achieved using an off the shelf PCIe accelerator card by optimizing kernel throughput of a systolic array architecture with compiler pipelining of the OpenCL kernels, carefully mapping memories used during computation and adjusting the number of systolic nodes per compute unit to fully utilize the FPGA resources.
Exhibitor Forum: SYCL for OpenCL: Accelerate High-performance Software on GPUs, CPUs, FPGAs, and Other Processors Using Open Standards in C++
Date and Time: Wednesday, November 18, 3:30PM - 4:00PM Room: 12AB | Event Page Presenters: Andrew Richards - Codeplay
SYCL is the royalty-free, cross-platform abstraction layer that enables the development of applications and frameworks that build on the underlying concepts, portability and efficiency of OpenCL™, while adding the ease-of-use and flexibility of C++. For example, SYCL can provide single source development where C++ template functions can contain both host and device code to construct complex algorithms that use OpenCL acceleration – and then enable re-use of those templates throughout the source code of an application to operate on different types of data.
This talk will present SYCL as an open standard as well as demonstrate implementations of SYCL and show how using C++ and open standards can deliver huge performance, quickly and easily across a range of hardware platforms.
Bridging OpenCL and CUDA: A comparative analysis and translation
Date & Time: Thursday, November 19, 4:00PM - 4:30PM Room: 18AB Session Chair: Dries Kimpe Authors: Junghyun Kim, Thanh Tuan Dao, Jaehoon Jung, Jinyoung Joo, Jaejin Lee all from Seoul National University
Heterogeneous systems are widening their user-base, and heterogeneous computing is becoming popular in supercomputing. Among others, OpenCL and CUDA are the most popular programming models for heterogeneous systems. Although OpenCL inherited many features from CUDA and they have almost the same platform model, they are not compatible with each other. In this paper, we present similarities and differences between them and propose an automatic translation framework for both OpenCL to CUDA and CUDA to OpenCL. We describe features that make it difficult to translate from one to the other and provide our solution. We show that our translator achieves comparable performance between the original and target applications in both directions. Since each programming model separately has a wide user-base and large code-base, our translation framework is useful to extend the code-base for each programming model and unifies the efforts to develop applications for heterogeneous systems.
Khronos Members and Associates Exhibiting at SC’15