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SC14 New Orleans
November 16-21, 2014
Ernest N. Morial Convention Center, New Orleans

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The LLVM Compiler Infrastructure in HPC

Monday, Nov 17 | All day
Gordon Brown, Codeplay

A talk held in conjunction with SC14 on how Codeplay leverages LLVM to implement SYCL. This talk will focus on the implementation approaches we use for Codeplay's SYCL implementation.

More information and calendar links.

Tutorial: OpenCL: A Hands-on Introduction

Monday, Nov 17 | 8:30am - 5:00pm | Room 395
Tim Mattson, Alice Koniges, and Simon McIntosh–Smith

The tutorial format will be a 50/50 split between lectures and exercises. Students will use their own laptops (Windows, Linux or OS/X) and log into a remote server running an OpenCL platform. Alternatively, students can load OpenCL onto their own laptops prior to the course (Intel, AMD and NVIDIA provide OpenCL SDKs. Apple laptops with X-code include OpenCL by default. Be sure to configure X-code to use the command line interface).

More information and calendar links.


Tuesday, Nov 18 | 12:15pm - 1:15PM | Room 283-84-85
Andrew Richards, Codeplay

Aa brief overview of all the ways Codeplay makes use of the LLVM open-source projects to implement a range of OpenCL technologies for customers

More information and calendar links.

OpenCL BOF: OpenCL Version 2.0 and Beyond

Tuesday, Nov 18 | 5:30pm – 7:00pm | Room 275-76-77
Tim Mattson, Simon McIntosh–Smith, Andrew Richards, Ronan Keryell, and others.

In this BOF, we will discuss the latest developments in OpenCL including the recent OpenCL 2.0 specification. We will then convene a panel representing divergent views on the future of OpenCL to engage in an interactive debate on where to take OpenCL.

More information and calendar links.

Poster Reception: Hardware Accelerated Linear Programming: Parallelizing the Simplex Method with OpenCL

Nov 16-21 | 5:15pm - 7:00pm | Room: New Orleans Theater Lobby

This work proposes an energy-efficient hardware accelerated Linear Programming (LP) solver. The system is based on the Simplex Algorithm for solving LP problems and is operable on Field Programmable Gate Arrays (FPGAs), Graphic Processing Units (GPUs), and Multi-Core Computer Processors (CPUs).

More information and calendar links.

Khronos Members Exhibiting at SC14


Complete floor plan is available here.

Click here to View or download a PDF of all Khronos members on the show floor.

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