The Khronos Group - Connecting Software to Silicon

The Khronos Group is a not for profit industry consortium creating open standards for the authoring and acceleration of parallel computing, graphics, dynamic media, computer vision and sensor processing on a wide variety of platforms and devices. All Khronos members are able to contribute to the development of Khronos API specifications, are empowered to vote at various stages before public deployment, and are able to accelerate the delivery of their cutting-edge 3D platforms and applications through early access to specification drafts and conformance tests.

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      Khronos technology at Super Computing SC12

      Date: November 10-16, 2012
      Location: Salt Lake City, Utah
      Venue: Salt Palace Convention Center
      Website: http://sc12.supercomputing.org/

      Schedule

      Improved OpenCL Programmability with clUtil

      SESSION: Research Poster Reception

      EVENT TYPE: Poster and Electronic Poster

      DATE/TIME: Tuesday Novemer 13th, 5:15PM - 7:00PM

      SESSION CHAIR: Torsten Hoefler

      AUTHOR(S): Rick Weber, Gregory D. Peterson

      ROOM: East Entrance

      ABSTRACT:
      CUDA was the first GPGPU programming environment to achieve widespread adoption and interest. This API owes much of its success to its highly productive abstraction model while still exposing enough hardware details to achieve high performance. OpenCL sacrifices much of the programmability in its front-end API for portability; while a less productive API than CUDA, it supports many more devices. In this poster, we present clUtil, which aims to reunite OpenCL's portability and CUDA's ease of use via C++11 language features. Furthermore, clUtil supports high-level parallelism motifs, namely a parallel-for loop that can automatically load balance applications onto heterogeneous OpenCL devices.

      CHAIR/AUTHOR DETAILS:

      • Torsten Hoefler (Chair) - ETH Zurich
      • Rick Weber - University of Tennessee, Knoxville
      • Gregory D. Peterson - University of Tennessee, Knoxville

      OpenCL: Supporting Mainstream Heterogeneous Computing

      SESSION: OpenCL: Supporting Mainstream Heterogeneous Computing

      EVENT TYPE: Birds of a Feather

      DATE/TIME: Wednesday November 14th, 5:30PM - 7:00PM

      SESSION LEADER(S): Timothy G. Mattson, Simon McIntosh-Smith, Ben Gaster

      ROOM: Ballroom-A

      ABSTRACT:
      OpenCL is an industry standard for programming heterogeneous computers (e.g. CPUs + GPUs). If you do heterogeneous computing and you don’t want to be locked into a single vendor’s products, you need to learn about OpenCL. At this BOF, we will share the latest developments in OpenCL. More importantly, however, we will launch the OpenCL user’s group. This group will be an independent community of users who use OpenCL, build OpenCL tools, and want to influence the evolution of OpenCL. Attend this BOF so you can get in on the ground floor of this exciting new development in OpenCL.

      SESSION LEADER DETAILS:

      An OpenCL Application for FPGAs

      SESSION: Heterogeneous Computing II

      EVENT TYPE: Exhibitor Forum

      DATE/TIME: Thursday November 15th, 10:30AM - 11:00AM

      PRESENTER(S):Desh Singh

      ROOM: 155-B

      ABSTRACT:
      OpenCL is a framework that enables programmers to produce massively parallel software in C. OpenCL has been adopted by CPU and GPU developers as a way to accelerate their hardware by exploiting parallelism on their chip. FPGAs by their nature are fine-grained, massively parallel arrays that process information in a significantly different manner from traditional CPU- or GPU-based systems and are a natural hardware platform to target an OpenCL program. OpenCL and the parallelism of FPGAs enable a new level of hardware acceleration and faster time-to-market for heterogeneous systems. During this presentation, Altera will show how OpenCL is being used by customers to map data parallel algorithms to FPGA-based devices and achieve high-performance FPGA applications in a fraction of the time. We will also show how to transform initial code that is functionally correct into a highly optimized implementation that maximizes the throughput on the FPGA.

      CHAIR/PRESENTER DETAILS:

      Khronos Members Exhibiting at SC12

      Complete floor plan is available here.

      AMD - Booth 2019

      Altera Corporation - Booth 430

      ARM - Booth 122

      Fujitsu - Booth 1709

      Intel - Booth 1925, 2511, 2601, 2617

      KISTI - Booth 3429

      NVIDIA - Booth 2217, 4466

      Samsung - Booth 721

      Texas Instruments - Booth 4828

       

       

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